Fujitsu CM8063501293407 manuales

Fujitsu CM8063501293407 Ficha de datos (236 paginas)

Marca: Fujitsu | Categoria: Procesadores | Tamaño: 4.59 MB |

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Tabla de contenidos

Processor E5-1600/E5

1

Table of Contents

3

Datasheet Volume One of Two

4

Revision History

10

1 Overview

11

Processor

14

1.1.2 Supported Technologies

16

1.2 Interfaces

17

1.2.2 PCI Express*

18

Transaction

19

1.2.4 Intel

20

1.3 Power Management Support

21

1.5 Package Summary

22

1.6 Terminology

22

1.7 Related Documents

25

1.9 State of Data

25

2 Interfaces

27

2.2 PCI Express* Interface

28

2.2.1.1 Transaction Layer

29

2.2.1.2 Data Link Layer

29

2.2.1.3 Physical Layer

29

2.4 Intel

30

2.5.1.1 Thermal Management

32

2.5.2 Client Command Suite

33

Reserved

34

# of Domains

34

Byte# 5

34

2.5.2.3 GetTemp()

35

2.5.2.4 RdPkgConfig()

37

2.5.2.5 WrPkgConfig()

38

Channel Temperature Data

45

816232431

45

DRAM Power Limit Performance

47

CPU ID Data

51

CPU code patch revision

52

Current Config Limit Data

57

RESERVED

57

Accumulated Energy Status

58

Accumulated CPU Energy

58

Accumulated CPU Throttle Time

60

2.5.2.7 RdIAMSR()

62

Cores 0,1,2...12

63

Thread (0,1) Mask for Core10

63

2.5.2.8 RdPCIConfig()

66

2.5.2.9 RdPCIConfigLocal()

67

DeviceBus Function Register

68

2.5.2.10 WrPCIConfigLocal()

69

2.5.3.1 Power-up Sequencing

71

2.5.3.2 Device Discovery

72

2.5.3.3 Client Addressing

72

2.5.3.4 C-states

73

2.5.3.5 S-states

74

2.5.3.6 Processor Reset

74

2.5.4 Multi-Domain Commands

76

2.5.5.1 Abort FCS

77

2.5.5.2 Completion Codes

77

2.5.7.1 Format

78

2.5.7.2 Interpretation

78

3 Technologies

81

3.1.2 Intel

82

VT-x Features

82

3.1.3 Intel® VT-d Objectives

82

3.2 Security Technologies

83

3.2.3 AES Instructions

84

3.3 Intel

85

Secure Key

85

3.4 Intel

85

OS Guard

85

3.6 Intel

86

Turbo Boost Technology

86

3.10 Intel

88

Dynamic Power Technology

88

4 Power Management

89

Table 4-6. Intel® QPI States

91

4.2.2 Low-Power Idle States

92

C1 C1E C6C3

93

4.2.4.1 Core C0 State

94

4.2.4.2 Core C1/C1E State

94

4.2.4.3 Core C3 State

95

4.2.4.4 Core C6 State

95

4.2.4.5 Delayed Deep C-States

95

4.2.5.1 Package C0

97

4.2.5.2 Package C1/C1E

97

4.2.5.3 Package C2 State

98

4.2.5.4 Package C3 State

98

4.2.5.5 Package C6 State

98

4.3.1 CKE Power-Down

100

4.3.2.1 Self Refresh Entry

101

4.3.2.2 Self Refresh Exit

101

4.3.2.3 DLL and PLL Shutdown

101

5 Thermal Management

103

CASE_MAX_B

104

CC activation

105

Table 5-1. T

107

5.1.5 Thermal Metrology

113

5.2.1 Processor Temperature

114

Intel® Xeon® Processor E5

115

Design Guide

115

5.2.2.2 Clock Modulation

117

5.2.4 PROCHOT_N Signal

118

5.2.5 THERMTRIP_N Signal

118

Interface

120

6 Signal Descriptions

121

6.5 PECI Signal

125

6.7 JTAG and TAP Signals

125

Miscellaneous Signals

126

7 Electrical Specifications

131

BCLK{0/1}_DN)

132

7.1.6.1 PLL Power Supply

133

7.1.9.2 Decoupling Guidelines

134

contains further

135

Table 7-2. SVID Address Usage

137

7.2 Signal Group Summary

138

7.5 Mixing Processors

143

7.8 DC Specifications

145

Table 7-13. Processor V

148

Figure 7-3. Processor V

149

7.8.2.1 V

150

Overshoot Specifications

150

Time [us]

151

Unit Figure Notes

153

VHavg (mV)

157

250 + 0.5 (VHavg - 700)

157

550 + 0.5 (VHavg - 700)

157

7.9 Signal Quality

158

7.9.3 Intel

159

Specifications

159

7.9.5.3 Activity Factor

160

1.3335 V 0.2835 V 3 ns 5 ns

161

1.2600 V 0.210 V 5 ns 5 ns

161

8 Processor Land Listing

163

8.2 Listing by Land Number

187

9 Package Mechanical

213

Intel® Xeon®

219

9.8 Processor Materials

220

9.9 Processor Markings

220

10.1 Introduction

221

(Boxed 25.5 mm Tall Passive H

222

Keepout Zones

223

LEGEND, SHEETS 1 & 2 ONLY

224

2200 MISSION COLLEGE BLVD

225

P.O. BOX 58119

225

SANTA CLARA, CA 95052-8119

225

Bases Only

228

Support (ILM-RS)

232

°C. Meeting the

233

(Blade + 1U + 2U Rack)

234

10.4 Boxed Processor Contents

236

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