Fujitsu MB91F109 FR30 manuales

Fujitsu MB91F109 FR30 Manual de usuario (461 paginas)

Marca: Fujitsu | Categoria: No | Tamaño: 1.87 MB |

Inglés

Tabla de contenidos

MB91F109

1

Hardware Manual

1

How to Read This Manual

9

CONTENTS

11

CHAPTER 1 OVERVIEW

25

1.1 MB91F109 Characteristics

26

1.3 Outside Dimensions

31

QFP100-P-1414-1

32

EIAJ code:

32

Plastic LQFP with 100 pins

32

1.3 Outside Dimensions

33

Outside Dimensions (FBGA-112)

33

FPT-100P-M05

35

1.5 Pin Functions

38

(can be used as a port)

40

1.6 I/O Circuit Format

46

1.7 Memory Address Space

48

1.8 Handling of Devices

50

CHAPTER 2 CPU

53

2.1 CPU Architecture

54

2.2 Internal Architecture

55

2.3 Programming Model

57

CHAPTER 2 CPU

58

2.3.2 Special Registers

60

D1 D0 XX0

64

[Initial value]

64

20 19 18 17 16

65

[Initial value]

65

2.4 Data Structure

66

2.5 Word Alignment

67

2.6 Memory Map

68

2.7 Instruction Overview

70

2.8.1 EIT Interrupt Levels

78

CPU via the bus

80

00000000

81

2.8.4 Interrupt Stack

82

000FFC00

83

2.8.6 EIT Vector Table

84

2.8.7 Multiple EIT Processing

86

2.8.8 EIT Operation

88

2.9 Reset Sequence

92

@@@@@@@@

93

MODR address: 0000 07FF

94

M1 M0 * * * * * * XXXXXXXX W

94

Bus mode setting bits

94

MODR writing

95

BW1 and BW0 of AMD0 to AMD5

95

Bus width specification

95

RSRR/WTCR STCR

98

PDRR CTBR

98

Control Register (WTCR)

100

07 06 05 04 03 02 01 00

102

00000481

102

000111-- R/W

102

Initial value

102

D3 D2 D1 D0 ----0000 R/W

104

15 14 13 12 11 10 09 08

104

00000482

104

00000483

105

AccessInitial value

105

00000484

106

110011-1 R/W

106

00000485

109

Initial value Access

109

SLCT1 SLCT0 VSTP 00--0--- R/W

110

3.9 Gear Function

111

3.10.1 Stop State

116

3.10.2 Sleep State

119

Standby Mode State Transition

122

3.11 Watchdog Function

123

3.13 DMA Suppression

127

3.14 Clock Doubler Function

129

CHAPTER 4 BUS INTERFACE

135

4.1 Outline of Bus Interface

136

4.2 Chip Select Area

139

4.3 Bus Interface

140

CHAPTER 4 BUS INTERFACE

144

76543210

145

MODR write

146

RSTX (reset)

146

Address: 0000 07FE

162

LE2 LE1 LE0 -----000 W

162

16-bit bus width

168

8-bit bus width

169

4.16.3 External Access

175

4.16.4 DRAM Relationships

179

4.17 Bus Timing

183

4.17.1 Basic Read Cycle

186

4.17.2 Basic Write Cycles

188

4.17.6 Automatic Wait Cycles

195

4.17.7 External Wait Cycles

196

4.17.16 Single DRAM Interface

211

4.17.19 Hyper DRAM Interface

214

4.17.20 DRAM Refresh

215

4.17.21 External Bus Request

217

CHAPTER 5 I/O PORTS

225

5.1 Outline of I/O Ports

226

5.2 Port Data Register (PDR)

227

CHAPTER 5 I/O PORTS

228

CONTROLLER

235

Interrupt request to

241

Input of interrupt

241

ILM setting

242

Address:00000430

244

DLYI -------0

245

(Initial value)

245

R R/W R/W R/W R/W

252

8.5 Priority Check

255

TBR default

256

Function (HRCR)

260

Incrementing PDRR

262

Clearing the interrupt cause

262

Decrementing PDRR

262

CHAPTER 9 U-TIMER

263

9.1 Overview of U-TIMER

264

9.2 U-TIMER Registers

265

9.3 U-TIMER Operation

267

CHAPTER 9 U-TIMER

268

CHAPTER 10 UART

269

10.1 Overview of UART

270

Register (SODR)

276

10.6 UART Operation

279

10.8 CLK Synchronous Mode

282

D6 D7 Stop

284

PE, ORE, FRE

284

Reception interrupt

284

Address/

285

SO SI SO SI

287

Host CPU

287

Slave CPU#0 Slave CPU#1

287

CHAPTER 10 UART

288

11.3 Data Register (ADCR)

299

11.4 A/D Converter Operation

300

• Internal clock operation

311

• Underflow operation

311

12.5 Counter States

313

CHAPTER 13 BIT SEARCH MODULE

315

CHAPTER 13 BIT SEARCH MODULE

322

CHAPTER 14 PWM TIMER

323

14.1 Overview of PWM Timer

324

14.2 PWM Timer Block Diagram

326

14.2 PWM Timer Block Diagram

327

14.9 PWM Operation

339

14.10 One-Shot Operation

341

14.11 Interrupt

343

CHAPTER 15 DMAC

347

15.1 Overview of DMAC

348

31 7 6 0

350

00000200H

350

Initial value: 0000000

350

Initial value: Undefined

350

15.6 DMAC Transfer Modes

359

End signals

362

15.8 Notes on DMAC

363

15.9 DMAC Timing Charts

366

CHAPTER 15 DMAC

370

CHAPTER 16 FLASH MEMORY

375

Flash memory status register

376

CHAPTER 16 FLASH MEMORY

378

Block Diagram of Flash Memory

378

Undefined

379

Undefined Undefined

379

(Undefined)

388

APPENDIX

393

APPENDIX A I/O Maps

394

D.1 C Compiler (fcc911)

419

D.2 Assembler (fasm911)

419

D.3 Linker (flnk911)

419

D.1 C Compiler (fcc911)

420

D.2 Assembler (fsm911)

423

D.3 Linker (flnk911)

425

APPENDIX E Instructions

427

APPENDIX E Instructions

428

6) Indicates flag changes

428

OP rel11

432

E.1 FR-Series Instructions

433

Electronic Devices

459

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