Fujitsu F2MCTM-16LX Manual de usuario Pagina 1

FUJITSU SEMICONDUCTORCONTROLLER MANUALF2MCTM-16LX16-BIT MICROCONTROLLERMB90360 SeriesHARDWARE MANUALCM44-10136-1E

vi CHAPTER 4 DELAYED INTERRUPT GENERATION MODULE ... 834.1 Overview of Delayed Interrupt Generation Module ...

84CHAPTER 4 DELAYED INTERRUPT GENERATION MODULE4.1 Overview of Delayed Interrupt Generation ModuleThe delayed interrupt generation module generates t

85CHAPTER 4 DELAYED INTERRUPT GENERATION MODULE4.2 Block Diagram of Delayed Interrupt Generation ModuleThe delayed interrupt generation module consis

86CHAPTER 4 DELAYED INTERRUPT GENERATION MODULE4.3 Configuration of Delayed Interrupt Generation ModuleThis section lists registers and reset values

87CHAPTER 4 DELAYED INTERRUPT GENERATION MODULE4.3.1 Delayed interrupt request generate/cancel register (DIRR)The delayed interrupt request generate/

88CHAPTER 4 DELAYED INTERRUPT GENERATION MODULE4.4 Explanation of Operation of Delayed Interrupt Generation ModuleThe delayed interrupt generation mo

89CHAPTER 4 DELAYED INTERRUPT GENERATION MODULE4.5 Precautions when Using Delayed Interrupt Generation ModuleThis section explains the precautions wh

90CHAPTER 4 DELAYED INTERRUPT GENERATION MODULE4.6 Program Example of Delayed Interrupt Generation ModuleThis section gives a program example of the

91CHAPTER 5CLOCKSThis chapter explains the clocks used by MB90360 series microcontrollers.5.1 Clocks5.2 Block Diagram of the Clock Generation Block5

92CHAPTER 5 CLOCKS5.1 ClocksThe clock generation block controls the operation of the internal clock that controls operation of the CPU and peripheral

93CHAPTER 5 CLOCKS●Machine clockThe machine clock controls the operation of the CPU and peripheral functions. One cycle of machine clockis regarded a

viiCHAPTER 9 MEMORY ACCESS MODES ... 1619.1 Outline of Memory Access Modes ...

94CHAPTER 5 CLOCKS Clock Supply MapSince the machine clock generated in the clock generation block is supplied as the clock that controls theoperati

95CHAPTER 5 CLOCKS5.2 Block Diagram of the Clock Generation BlockThe clock generation block consists of five blocks:• System clock generation circuit

96CHAPTER 5 CLOCKS●Oscillation clock generation circuitThis circuit generates an oscillation clock (HCLK) by connecting an oscillator or inputting an

97CHAPTER 5 CLOCKS5.2.1 Register of Clock Generation BlockThis section explains the register of the clock generation block. Clock Selection Register

98CHAPTER 5 CLOCKS5.3 Clock Selection Register (CKSCR)The clock selection register (CKSCR) is used to switch among the main clock, PLL clocks and sub

99CHAPTER 5 CLOCKSTable 5.3-1 Functions of Clock Selection Register (CKSCR) (1/2)Bit name Functionbit15 SCM: Sub clock operation flag bitThe bit ind

100CHAPTER 5 CLOCKSbit10 MCS: PLL clock select bitThis bit indicates the main clock or PLL clock to be selected as the machine clock.When the machine

101CHAPTER 5 CLOCKS5.4 PLL/Subclock Control Register (PSCCR)PLL/Subclock control register selects the PLL multiplication rate and subclock division r

102CHAPTER 5 CLOCKSTable 5.4-1 Functional Description of Each Bit in the PLL/subclock Control Register (PSCCR)Bit name Functionbit15tobit12 Unused T

103CHAPTER 5 CLOCKS5.5 Clock ModeThree clock modes are provided: main clock mode, PLL clock mode and sub-clock mode. Clock Mode●Main clock modeIn ma

viii 13.5 Explanation of Operation of 16-bit Free-run Timer ... 22913.6 Expla

104CHAPTER 5 CLOCKS●Transition from sub-clock mode to main clock modeWhen the SCS bit of the clock selection register (CKSCR) is rewritten from “0” t

105CHAPTER 5 CLOCKSFigure 5.5-1 shows the status change caused by machine clock switching.Figure 5.5-1 Status Change Diagram for Machine Clock Selec

106CHAPTER 5 CLOCKSNotes:• The initial value for the machine clock setting is main clock (CKSCR: MCS = 1, SCS = 1).• If both the SCS and MCS bits are

107CHAPTER 5 CLOCKS5.6 Oscillation Stabilization Wait IntervalWhen the power is turned on during the oscillation clock is stopped or when stop mode i

108CHAPTER 5 CLOCKS5.7 Connection of an Oscillator or an External Clock to the MicrocontrollerThe MB90360 series microcontroller contains a system cl

109CHAPTER 6CLOCK SUPERVISORThis chapter explains the function and the operation of the clock supervisor. Only the product with built-in clock supervi

110CHAPTER 6 CLOCK SUPERVISOR6.1 Overview of Clock SupervisorThe clock supervisor checks the oscillation of the main clock or a sub-clock (without &q

111CHAPTER 6 CLOCK SUPERVISOR6.2 Block Diagram of Clock SupervisorThe clock Supervisor is composed of the following block:• Main clock supervisor• Su

112CHAPTER 6 CLOCK SUPERVISOR●Main clock supervisorThe oscillation of the main oscillation clock (HCLK) is supervised by using the clock from theCR o

113CHAPTER 6 CLOCK SUPERVISOR6.3 Clock Supervisor Control Register (CSVCR)This register switches main clock/sub clock/PLL clock, and selects the osci

ixCHAPTER 17 DTP/EXTERNAL INTERRUPTS ... 31317.1 Overview of DTP/External Interrupt ...

114CHAPTER 6 CLOCK SUPERVISORBit name Functionbit7 SCKS Sub clock selectThis bit permits built-in CR oscillation clock to be used as a sub-clock. Onl

115CHAPTER 6 CLOCK SUPERVISOR6.4 Operating Mode of Clock SupervisorThis section explains all the operating modes of the Clock Supervisor. Operating

116CHAPTER 6 CLOCK SUPERVISOR• The sub-clock supervisor is operated by setting SSVE(CSVCR:bit2) to 1. Please note the programmingof software to do af

117CHAPTER 6 CLOCK SUPERVISOR Reset Check By Clock SupervisorTo check whether reset was executed by the clock supervisor, the WDTC register is read

118CHAPTER 6 CLOCK SUPERVISOR

119CHAPTER 7RESETSThis chapter describes resets for the MB90360-series microcontrollers.7.1 Resets7.2 Reset Cause and Oscillation Stabilization Wait

120CHAPTER 7 RESETS7.1 ResetsIf a reset is generated, the CPU immediately stops the current execution process and waits for the reset to be cleared.

121CHAPTER 7 RESETSstabilization wait time has elapsed, the reset is executed.●External resetAn external reset is generated by the L level input to a

122CHAPTER 7 RESETS●CPU operation detection resetThe CPU operation detection reset is 20-bit counter that the source oscillation is count-locked. If

123CHAPTER 7 RESETS7.2 Reset Cause and Oscillation Stabilization Wait TimesThe MB90360 series has seven reset causes. The oscillation stabilization w

x 20.4.2 LIN-UART Serial Mode Register (SMR) ... 39520.4.3 Serial

124CHAPTER 7 RESETSFigure 7.2-1 Oscillation Stabilization Wait Times at a Power-on ResetNote:Ceramic and crystal oscillators generally require an os

125CHAPTER 7 RESETS7.3 External Reset PinThe external reset pin (RST pin) is an input pin used exclusively for a reset. Inputting an L level signal g

126CHAPTER 7 RESETS7.4 Reset OperationWhen the reset signal is inactivated, the reset vector and mode data is fetched from the predetermined location

127CHAPTER 7 RESETS Mode FetchWhen the reset is cleared, the CPU transfers the reset vector and the mode data to the appropriate registersin the CPU

128CHAPTER 7 RESETS7.5 Reset Cause BitsA reset cause can be identified by reading the watchdog timer control register (WDTC). Reset Cause BitsAs sho

129CHAPTER 7 RESETS Correspondence between reset cause bits and reset causesFigure 7.5-2 shows the configuration of the reset cause bits of the watc

130CHAPTER 7 RESETS Status of Reset Cause Bit and Low Voltage Detection BitFigure 7.5-3 Status of Reset Cause Bit and Low Voltage Detection Bit*: T

131CHAPTER 7 RESETS Notes about Reset Cause Bits●Multiple reset causes generated at the same timeWhen multiple reset causes are generated at the sam

132CHAPTER 7 RESETS7.6 Status of Pins in a ResetThis section describes the status of pins when a reset occurs. Status of Pins during a ResetThe stat

133CHAPTER 8LOW-POWERCONSUMPTION MODEThis chapter explains the low-power consumption mode of MB90360 series microcontrollers.8.1 Overview of Low-Powe

xi21.4.20 Reception Interrupt Enable Register (RIER) ... 47621.4.21 Accept

134CHAPTER 8 LOW-POWER CONSUMPTION MODE8.1 Overview of Low-Power Consumption ModeThe MB90360 series has the following CPU operating modes, any of whi

135CHAPTER 8 LOW-POWER CONSUMPTION MODE Clock Mode●PLL clock modeIn this mode, a PLL clock that is a multiple of the oscillation clock (HCLK) is use

136CHAPTER 8 LOW-POWER CONSUMPTION MODE●Timebase timer modeThe timebase timer mode operates the oscillation clock (HCLK), sub-clock (SCLK), timebase

137CHAPTER 8 LOW-POWER CONSUMPTION MODE8.2 Block Diagram of the Low-Power Consumption Control CircuitThis section shows the block diagram of the low-

138CHAPTER 8 LOW-POWER CONSUMPTION MODE●CPU clock control circuitThis circuit controls clocks supplied to the CPU. ●Pin high-impedance control circui

139CHAPTER 8 LOW-POWER CONSUMPTION MODE8.3 Low-Power Consumption Mode Control Register (LPMCR)This register switches to or releases the low-power con

140CHAPTER 8 LOW-POWER CONSUMPTION MODETable 8.3-1 Functions of Low-power Consumption Mode Control Register (LPMCR)Bit name Functionbit7 STP:Stop mo

141CHAPTER 8 LOW-POWER CONSUMPTION MODENotes:• Switching to a low-power consumption mode is performed by writing the low-power consumption modecontro

142CHAPTER 8 LOW-POWER CONSUMPTION MODE8.4 CPU Intermittent Operation ModeThis mode is used for intermittent operation of the CPU while operation clo

143CHAPTER 8 LOW-POWER CONSUMPTION MODE8.5 Standby ModeThe standby mode causes the standby control circuit to either stop supplying an operation cloc

xii CHAPTER 25 EXAMPLES OF MB90F362/T(S), MB90F367/T(S)SERIAL PROGRAMMING CONNECTION ...

144CHAPTER 8 LOW-POWER CONSUMPTION MODE❍: operation, ✕: stop, ◆: held in the state before transiting, Hi-Z: High impedance*1 : The timebase timer, wa

145CHAPTER 8 LOW-POWER CONSUMPTION MODE8.5.1 Sleep ModeThis mode causes the CPU operating clock to stop during operation in each clock mode. The CPU

146CHAPTER 8 LOW-POWER CONSUMPTION MODE●Operation during an interrupt requestWriting 1 in the SLP bit of the low-power consumption mode control regis

147CHAPTER 8 LOW-POWER CONSUMPTION MODEFigure 8.5-1 Release of Sleep Mode by Interrupt OccurrenceNote:When interrupt processing is executed, the CPU

148CHAPTER 8 LOW-POWER CONSUMPTION MODE8.5.2 Watch ModeThis mode causes all functions, excluding the subclock (SCLK), watch timer, and low voltage de

149CHAPTER 8 LOW-POWER CONSUMPTION MODEidentified according to the settings of the I flag in the condition code register (CCR), the interruptlevel ma

150CHAPTER 8 LOW-POWER CONSUMPTION MODE8.5.3 Timebase Timer ModeThis mode causes all functions, excluding oscillation clock (HCLK), subclock (SCLK),

151CHAPTER 8 LOW-POWER CONSUMPTION MODE●Return by interruptWhen an interrupt request higher than interrupt level (IL) of 7 is generated from the watc

152CHAPTER 8 LOW-POWER CONSUMPTION MODE8.5.4 Stop ModeBecause this mode causes oscillation clock (HCLK) and subclock (SCLK) to stop during operation

153CHAPTER 8 LOW-POWER CONSUMPTION MODE●Status of pinsWhether the I/O pins in the stop mode retain the state they had immediately before switching to

1CHAPTER 1OVERVIEWThe MB90360 Series is a family member of the F2MC-16LX micro controllers.1.1 Overview of MB903601.2 Block Diagram of MB90360 serie

154CHAPTER 8 LOW-POWER CONSUMPTION MODE●Return by interruptWhen an interrupt request higher than the interrupt level (IL) of 7 is generated from exte

155CHAPTER 8 LOW-POWER CONSUMPTION MODE8.6 Status Change DiagramFigure 8.6-1 shows the operation status and status transition in the clock mode and s

156CHAPTER 8 LOW-POWER CONSUMPTION MODE8.7 Status of Pins in Standby Mode and during Hold and ResetThe status of I/O pins in the standby mode and dur

157CHAPTER 8 LOW-POWER CONSUMPTION MODE8.8 Usage Notes on Low-Power Consumption ModeThis section explains the notes when using the low-power consumpt

158CHAPTER 8 LOW-POWER CONSUMPTION MODE●PLL clock oscillation stabilization wait timeIn main clock mode, the PLL multiplication circuit stops. When c

159CHAPTER 8 LOW-POWER CONSUMPTION MODEThe devices does not guarantee its operation after returning from the standby mode if you place an arrayof ins

160CHAPTER 8 LOW-POWER CONSUMPTION MODE

161CHAPTER 9MEMORY ACCESS MODESThis chapter explains the functions and operations of the memory access modes.9.1 Outline of Memory Access Modes

162CHAPTER 9 MEMORY ACCESS MODES9.1 Outline of Memory Access ModesIn the F2MC-16LX, various modes are provided for access methods and access areas.

163CHAPTER 9 MEMORY ACCESS MODES9.1.1 Mode PinsTable 9.1-2 lists the operations that can be specified by combining the three external pins MD2 to MD0

2CHAPTER 1 OVERVIEW1.1 Overview of MB90360The MB90360 Series is a 16-bit microcontroller designed for automotive applications and contains CAN functi

164CHAPTER 9 MEMORY ACCESS MODES9.1.2 Mode DataMode data is stored at FFFFDFH of main memory and used for controlling the CPU operation. This data is

165CHAPTER 9 MEMORY ACCESS MODES9.1.3 Memory Space in Each Bus ModeFigure 9.1-2 shows the correspondence between the access areas and physical addres

166CHAPTER 9 MEMORY ACCESS MODES Recommended SettingTable 9.1-4 lists an example of recommended settings for mode pins and mode data.External pins h

167CHAPTER 10I/O PORTSThis chapter explains the functions and operations of the I/O ports.10.1 I/O Ports10.2 I/O Port Registers

168CHAPTER 10 I/O PORTS10.1 I/O PortsEach pin of the ports can be specified as input or output using the port direction register (DDR) if the corresp

169CHAPTER 10 I/O PORTS10.2 I/O Port RegistersThere are five types of I/O port registers:• Port data register (PDR2, PDR4 to PDR6, PDR8)• Port direct

170CHAPTER 10 I/O PORTS10.2.1 Port Data Register (PDR)Note that R/W for I/O ports differ from R/W for memory in the following points:• Input modeRead

171CHAPTER 10 I/O PORTS●Reading the port data registerThe value obtained when reading the port data register (PDR) depends on the status of the port

172CHAPTER 10 I/O PORTS10.2.2 Port Direction Register (DDR)This register has following functions: • Setting the data direction of each pin that is us

173CHAPTER 10 I/O PORTSNote:SIL0, SIL1 are write-only, and “1” is always read from these bits. Therefore, instructions that perform aread-modify-writ

3CHAPTER 1 OVERVIEW●CPU-independent automatic data transfer functionExtended intelligent I/O service (EI2OS): Maximum 16 channels●Lower-power consump

174CHAPTER 10 I/O PORTS10.2.3 Pull-up Control Register (PUCR)Each pin of port2 has programmable pull-up resistor. Each bit of this register controls

175CHAPTER 10 I/O PORTS10.2.4 Analog Input Enable Register (ADER)Figure 10.2-6 shows the analog input enable register. Analog Input Enable Registers

176CHAPTER 10 I/O PORTS10.2.5 Input Level Select RegisterThe input level select register allows to switch from Automotive Hysteresis input levels to

177CHAPTER 10 I/O PORTS Initial value of ILSRInitial value of each bit of ILSR is determined when external reset signal is released depending on the

178CHAPTER 10 I/O PORTS

179CHAPTER 11TIMEBASE TIMERThis chapter explains the functions and operations of the timebase timer.11.1 Overview of Timebase Timer11.2 Block Diagra

180CHAPTER 11 TIMEBASE TIMER11.1 Overview of Timebase TimerThe timebase timer is an 18-bit free-run counter (timebase timer counter) that increments

181CHAPTER 11 TIMEBASE TIMER Clock SupplyThe timebase timer supplies an operation clock to the resources such as an oscillation stabilization waitti

182CHAPTER 11 TIMEBASE TIMER11.2 Block Diagram of Timebase TimerThe timebase timer consists of the following blocks:• Timebase timer counter• Counter

183CHAPTER 11 TIMEBASE TIMER●Timebase timer counterThe timebase timer counter is an 18-bit up counter that uses a clock with a half frequency of the

4CHAPTER 1 OVERVIEW●Delayed interrupt generation moduleGenerates interrupt request for task switching●8-/10-bit A/D converter: 16 channels• 8-bit and

184CHAPTER 11 TIMEBASE TIMER11.3 Configuration of Timebase TimerThis section explains the registers and interrupt factors of the timebase timer. Lis

185CHAPTER 11 TIMEBASE TIMER11.3.1 Timebase timer control register (TBTC)The timebase timer control register (TBTC) provides the following settings:•

186CHAPTER 11 TIMEBASE TIMERTable 11.3-1 Functions of Timebase Timer Control Register (TBTC)Bit name Functionbit15 Reserved: reserved bit Always se

187CHAPTER 11 TIMEBASE TIMER11.4 Interrupt of Timebase TimerThe timebase timer generates an interrupt request (interval timer function) when the inte

188CHAPTER 11 TIMEBASE TIMER11.5 Explanation of Operations of Timebase Timer FunctionsThe timebase timer operates as an interval timer or an oscillat

189CHAPTER 11 TIMEBASE TIMERAt transition to the stop mode, the timebase timer counter is cleared to stop counting up. At return from thestop mode, t

190CHAPTER 11 TIMEBASE TIMER Operation as Oscillation Stabilization Wait Time TimerThe timebase timer can be used as the oscillation stabilization w

191CHAPTER 11 TIMEBASE TIMER Supply of Operation ClockThe timebase timer supplies an operation clock to the PPG timers and the watchdog timer.Note:C

192CHAPTER 11 TIMEBASE TIMER11.6 Precautions when Using Timebase TimerPrecautions when using the timebase timer are shown below. Precautions when Us

193CHAPTER 11 TIMEBASE TIMER11.7 Program Example of Timebase TimerProgramming examples for the timebase timer are shown below. Program Example of Ti

5CHAPTER 1 OVERVIEW Product overviewTable 1.1-1 Product Overview (1/2)FeaturesMB90362 MB90362T MB90362S MB90362TSMB90V340A-101MB90V340A-102CPUF2MC-

194CHAPTER 11 TIMEBASE TIMER DSL WARI ORG 0FFDCH ;Reset vector setting DSL START DB 00H

195CHAPTER 12WATCHDOG TIMERThis chapter describes the function and operation of the watchdog timer.12.1 Overview of Watchdog Timer12.2 Configuration

196CHAPTER 12 WATCHDOG TIMER12.1 Overview of Watchdog TimerThe watchdog timer is a 2-bit counter that uses the timebase timer or watch timer as a cou

197CHAPTER 12 WATCHDOG TIMERTable 12.1-1 Interval Time of Watchdog TimerMainClock cycleExamples calculatedExternal clock(@4MHz) CR oscillationMin. M

198CHAPTER 12 WATCHDOG TIMERNotes:• When the timebase timer output (carry signal) is used as a count clock to the watchdog timer, clearing the timeba

199CHAPTER 12 WATCHDOG TIMER12.2 Configuration of Watchdog TimerThe watchdog timer consists of the following blocks:• Count clock selector• Watchdog

200CHAPTER 12 WATCHDOG TIMER●Count clock selectorThe count clock selector selects a count clock input to the watchdog timer from the timebase timer o

201CHAPTER 12 WATCHDOG TIMER12.3 Watchdog Timer RegistersThis section explains the registers used for setting the watchdog timer. List of Registers

202CHAPTER 12 WATCHDOG TIMER12.3.1 Watchdog timer control register (WDTC)The watchdog timer control register starts and clears the watchdog timer, se

203CHAPTER 12 WATCHDOG TIMERTable 12.3-1 Functions of the Watching Timer Control Register (WDTC)Bit name Functionbit0bit1WT1, WT0:Interval time sele

6CHAPTER 1 OVERVIEWTable 1.1-2 Product Overview (2/2)FeaturesMB90367 MB90367T MB90367S MB90367TSMB90V340A-103MB90V340A-104CPUF2MC-16LX CPUSystem clo

204CHAPTER 12 WATCHDOG TIMER12.4 Explanation of Operations of Watchdog Timer FunctionsAfter starting, when the watchdog timer reaches the set interva

205CHAPTER 12 WATCHDOG TIMER●Clearing watchdog timer• When "0" is written once again to the watchdog timer control bit (WDTC: WTE) within t

206CHAPTER 12 WATCHDOG TIMER●Checking reset factorsThe reset factor bits in the watchdog timer control register (WDTC: PONR, WRST, ERST, SRST) can be

207CHAPTER 12 WATCHDOG TIMER12.5 Precautions when Using Watchdog TimerTake the following precautions when using the watchdog timer. Precautions when

208CHAPTER 12 WATCHDOG TIMER12.6 Program Examples of Watchdog TimerProgram example of watchdog timer is given below: Program Examples of Watchdog Ti

209CHAPTER 1316-Bit I/O TIMERThis chapter explains the function and operation of the 16- bit I/O timer.13.1 Overview of 16-bit I/O Timer13.2 Block D

210CHAPTER 13 16-Bit I/O TIMER13.1 Overview of 16-bit I/O TimerThe 16-bit I/O timer consists of one 16-bit free-run timer and 4 input capture. The ti

211CHAPTER 13 16-Bit I/O TIMER13.2 Block Diagram of 16-bit I/O TimerThe 16-bit I/O timer consists of the following modules:• 16-bit free-run timer• I

212CHAPTER 13 16-Bit I/O TIMER Details of Pins and Interrupt NumberTable 13.2-1 shows the pins used by the 16-bit details of interrupt.Table 13.2-1

213CHAPTER 13 16-Bit I/O TIMER13.2.1 Block Diagram of 16-bit Free-run TimerThe MB90360 series contains 1 channel of the 16-bit free-run timer, and it

7CHAPTER 1 OVERVIEW FeaturesTable 1.1-3 MB90360 Features (1/2)FeaturesMB90F362/T(S), MB90362/T(S)MB90F367/T(S), MB90367/T(S)MB90V340A-101, MB90V340

214CHAPTER 13 16-Bit I/O TIMER13.2.2 Block Diagram of Input CaptureThe input capture consist of the following blocks: Block Diagram of Input Capture

215CHAPTER 13 16-Bit I/O TIMER●Input capture data registers 0 to 3 (IPCP0 to IPCP3)• Input capture data register retains the counter value of the 16-

216CHAPTER 13 16-Bit I/O TIMER13.3 Configuration of 16-bit I/O TimerThis section explains the pins, registers, and interrupt factors of the 16-bit I/

217CHAPTER 13 16-Bit I/O TIMER13.3.1 Timer Control Status Register (Upper) (TCCSH)Timer control status register (upper) selects the count clock and t

218CHAPTER 13 16-Bit I/O TIMER13.3.2 Timer Control Status Register (Lower) (TCCSL)The timer control status register (Lower) selects the count clock a

219CHAPTER 13 16-Bit I/O TIMERTable 13.3-3 Functions of Timer Control Status Register (Lower) (TCCSL)Bit name Functionbit7 IVF: Timer overflow gener

220CHAPTER 13 16-Bit I/O TIMER13.3.3 Timer Data Register (TCDT)The timer data register is a 16-bit up counter.• The counter value of the 16-bit free-

221CHAPTER 13 16-Bit I/O TIMER13.3.4 Input Capture Control Status Registers (ICS)The function of the input capture control status register is shown b

222CHAPTER 13 16-Bit I/O TIMERTable 13.3-4 Functions of Input Capture Control Status Register (ICS)Bit name Functionbit7 ICPm: Valid edge detection

223CHAPTER 13 16-Bit I/O TIMER13.3.5 Input Capture Register (IPCP)Input capture register stores the counter value fetched from 16-bit free-run timer

8CHAPTER 1 OVERVIEWCAN interface1 channel 3 channelsConforms to CAN Specification Version 2.0 Part A and BAutomatic re-transmission in case of errorA

224CHAPTER 13 16-Bit I/O TIMER13.3.6 Input Capture Edge Register (ICE)The input capture edge register has a function to indicate the selected edge di

225CHAPTER 13 16-Bit I/O TIMERTable 13.3-5 Functions of Input Capture Edge Register 01 (ICE01) Bit name Functionbit15tobit13Undefined bits Read : Th

226CHAPTER 13 16-Bit I/O TIMERNote:In the input capture 0 and 1, if the input signal is selected to the LIN-UART (ICE01:ICUS), the input capture is u

227CHAPTER 13 16-Bit I/O TIMER13.4 Interrupts of 16-bit I/O TimerThe interrupt factors of the 16-bit I/O timer has overflow of the counter value in t

228CHAPTER 13 16-Bit I/O TIMER 16-bit I/O Timer Interrupt and EI2OSReference:For details of the interrupt number, interrupt control register, and in

229CHAPTER 13 16-Bit I/O TIMER13.5 Explanation of Operation of 16-bit Free-run TimerAfter a reset, the 16-bit free-run timer starts incrementing from

230CHAPTER 13 16-Bit I/O TIMERFigure 13.5-2 shows counter clearing at an overflow.Figure 13.5-2 Counter Clearing at an OverflowFFFFHBFFFH7FFFH3FFFH

231CHAPTER 13 16-Bit I/O TIMER13.6 Explanation of Operation of Input CaptureThe input capture stores the counter value of the 16-bit free-run timer t

232CHAPTER 13 16-Bit I/O TIMERFigure 13.6-2 Timing of Fetching Data for Input CaptureFigure 13.6-3 Operation of Input Capture (Rising edge/falling

233CHAPTER 13 16-Bit I/O TIMER13.7 Precautions when Using 16-bit I/O TimerThis section explains the precautions when using the 16-bit I/O timer. Pre

9CHAPTER 1 OVERVIEW1.2 Block Diagram of MB90360 seriesFigure 1.2-3 shows a block diagram of the MB90360. Block Diagram of Evaluation ChipFigure 1.2-

234CHAPTER 13 16-Bit I/O TIMER13.8 Program Example of 16-bit I/O TimerThis section gives a program example of the 16-bit I/O timer. Program Example

235CHAPTER 13 16-Bit I/O TIMER MOV I:ICS01,#00010001B ;IN0 pin selection, External trigger, ;IPCP0 rising edge

236CHAPTER 13 16-Bit I/O TIMER

237CHAPTER 1416-BIT RELOAD TIMERThis chapter describes the functions and operation of the 16-bit reload timer.14.1 Overview of the 16-bit Reload Time

238CHAPTER 14 16-BIT RELOAD TIMER14.1 Overview of the 16-bit Reload TimerThe 16-bit reload timer has the following functions:• The count clock can be

239CHAPTER 14 16-BIT RELOAD TIMER Operation at UnderflowWhen the start trigger is inputted, the value set in the 16-bit reload register (TMRLR) is r

240CHAPTER 14 16-BIT RELOAD TIMER14.2 Block Diagram of 16-bit Reload TimerThe 16-bit reload timers 2 and 3 composed of the following seven blocks:• C

241CHAPTER 14 16-BIT RELOAD TIMER●Details of pins in block diagramThere are two channels for 16-bit reload timer.The actual pin names, outputs to res

242CHAPTER 14 16-BIT RELOAD TIMER14.3 Configuration of 16-bit Reload TimerThis section explains the pins, registers, and interrupt factors of the 16-

243CHAPTER 14 16-BIT RELOAD TIMER 16-bit Reload Timer Registers and Reset Value●16-bit reload timer 2 registerFigure 14.3-1 List of 16-bit Reload T

10CHAPTER 1 OVERVIEWFigure 1.2-2 Block Diagram of Evaluation Chip (MB90V340A-103/104)(INT15R to INT8R)INT15 to INT8INT7 to INT0CKOTSCL1 , SCL0SDA1 ,

244CHAPTER 14 16-BIT RELOAD TIMER Generation of Interrupt Request from 16-bit Reload TimerWhen the 16-bit reload timer is started and the count valu

245CHAPTER 14 16-BIT RELOAD TIMER14.3.1 Timer Control Status Registers (High) (TMCSR:H)The timer control status registers (High) (TMCSR:H) set the op

246CHAPTER 14 16-BIT RELOAD TIMERTable 14.3-2 Functions of Timer Control Status Registers (High) (TMCSR: H)Bit name Functionbit15 to bit12Undefined

247CHAPTER 14 16-BIT RELOAD TIMER14.3.2 Timer Control Status Registers (Low) (TMCSR: L)The timer control status registers (Low) (TMCSR:L) enables or

248CHAPTER 14 16-BIT RELOAD TIMERTable 14.3-3 Timer Control Status Registers (Low) (TMCSR: L)Bit Name Functionbit6 OUTE: TOT pin Output enable bitTh

249CHAPTER 14 16-BIT RELOAD TIMER14.3.3 16-bit Timer Registers (TMR)The 16-bit timer registers are 16-bit down counters. At read, the value being cou

250CHAPTER 14 16-BIT RELOAD TIMER14.3.4 16-bit Reload Registers (TMRLR)The 16-bit reload registers set the value to be reloaded to the 16-bit timer r

251CHAPTER 14 16-BIT RELOAD TIMER14.4 Interrupts of 16-bit Reload TimerThe 16-bit reload timer generates an interrupt request when the 16-bit timer r

252CHAPTER 14 16-BIT RELOAD TIMER14.5 Explanation of Operation of 16-bit Reload TimerThis section explains the setting of the 16-bit reload timer and

253CHAPTER 14 16-BIT RELOAD TIMER Operating State of 16-bit Timer RegisterThe operating state of the 16-bit timer register is determined by the time

11CHAPTER 1 OVERVIEW Block Diagram of Flash/Mask ROM VersionFigure 1.2-3 Block Diagram of Flash/Mask ROM VersionAN15 to AN0Clockcontrol/monitor *3R

254CHAPTER 14 16-BIT RELOAD TIMER14.5.1 Operation in Internal Clock ModeIn the internal clock mode, three operation modes can be selected by setting

255CHAPTER 14 16-BIT RELOAD TIMER Operation as 16-bit Timer Register UnderflowsWhen the value of the 16-bit timer register (TMR) is decremented from

256CHAPTER 14 16-BIT RELOAD TIMERFigure 14.5-4 Count Operation in Software Trigger Mode (One-shot Mode)Figure 14.5-5 Count Operation in Software Tr

257CHAPTER 14 16-BIT RELOAD TIMER [External trigger mode (MOD2 to MOD0="001B", "010B", "011B")]When the external trigge

258CHAPTER 14 16-BIT RELOAD TIMER [External gate input mode (MOD2 to MOD0="1x0B", "1x1B")]When the external gate input mode is se

259CHAPTER 14 16-BIT RELOAD TIMER14.5.2 Operation in Event Count ModeIn the event count mode, after the 16-bit reload timer is started, the edge of t

260CHAPTER 14 16-BIT RELOAD TIMER Operation as 16-bit Timer Register UnderflowsWhen the value of the 16-bit timer register (TMR) is decremented from

261CHAPTER 14 16-BIT RELOAD TIMER Operation in Event Count ModeThe operation of the 16-bit reload timer is enabled by setting the timer operation en

262CHAPTER 14 16-BIT RELOAD TIMER14.6 Precautions when Using 16-bit Reload TimerThis section explains the precautions when using the 16-bit reload ti

263CHAPTER 14 16-BIT RELOAD TIMER14.7 Sample Program of 16-bit Reload TimerThis section gives a program example of the 16-bit reload timer operated i

12CHAPTER 1 OVERVIEW1.3 Package DimensionsMB90360 series has a package.Note that the dimensions show below are reference dimensions. For formal dimen

264CHAPTER 14 16-BIT RELOAD TIMER BRA LOOP ;;---------Interrupt program-----------------------------------WARI: CLR I:UF2

265CHAPTER 14 16-BIT RELOAD TIMER AND CCR,#0BFH ;Interrupts disabled MOV I:ICR04,#00H ;Interrupt level 0 (highest) MOV I:

266CHAPTER 14 16-BIT RELOAD TIMER

267CHAPTER 15WATCH TIMERThis chapter describes the functions and operations of the watch timer.15.1 Overview of Watch Timer15.2 Block Diagram of Wat

268CHAPTER 15 WATCH TIMER15.1 Overview of Watch TimerThe watch timer is a 15-bit free-run counter that increments in synchronization with the subcloc

269CHAPTER 15 WATCH TIMER Cycle of Clock SupplyThe watch timer supplies an operation clock to the oscillation stabilization wait time timer of the s

270CHAPTER 15 WATCH TIMER15.2 Block Diagram of Watch TimerThe watch timer consists of the following blocks:• Watch timer counter• Counter clear circu

271CHAPTER 15 WATCH TIMER●Interval timer selectorThe interval timer selector sets the overflow flag bit when the watch timer counter reaches the inte

272CHAPTER 15 WATCH TIMER15.3 Configuration of Watch TimerThis section explains the registers and interrupt factors of the watch timer. List of Regi

273CHAPTER 15 WATCH TIMER15.3.1 Watch Timer Control Register (WTC)This section explains the functions of the watch timer control register (WTC). Wat

13CHAPTER 1 OVERVIEW1.4 Pin AssignmentThis section shows the pin assignments for the MB90360 series. Pin assignment (LQFP-48)Figure 1.4-1 shows the

274CHAPTER 15 WATCH TIMERTable 15.3-1 Functions of Watch Timer Control Register (WTC)Bit Name Functionbit7 WDCS: Watchdog clock select bitThis bit s

275CHAPTER 15 WATCH TIMER15.4 Watch Timer InterruptWhen the interval time is reached with the watch timer interrupt enabled, the overflow flag bit is

276CHAPTER 15 WATCH TIMER15.5 Explanation of Operation of Watch TimerThe watch timer operates as an interval timer or an oscillation stabilization wa

277CHAPTER 15 WATCH TIMER●Clearing overflow flag bit (WTC:WTOF)When the mode is switched to the stop mode, the watch timer is used as an oscillation

278CHAPTER 15 WATCH TIMER15.6 Program Example of Watch TimerThis section gives a program example of the watch timer. Program Example of Watch Timer●

279CHAPTER 15 WATCH TIMER ORG 00FFDCH ;Reset vector set DSL START DB 00H ;Set to single-chip modeV

280CHAPTER 15 WATCH TIMER

281CHAPTER 168-/16-BIT PPG TIMERThis chapter describes the functions and operations of the 8-/16-bit PPG timer.16.1 Overview of 8-/16-bit PPG Timer16

282CHAPTER 16 8-/16-BIT PPG TIMER16.1 Overview of 8-/16-bit PPG TimerThe 8-/16-bit PPG timer is a reload timer module with two channels (PPGC and PPG

283CHAPTER 16 8-/16-BIT PPG TIMER Operation Modes of 8-/16-bit PPG Timer●8-bit PPG output 2-channel independent operation modeThe 8-bit PPG output 2

FUJITSU LIMITEDF2MCTM-16LX16-BIT MICROCONTROLLERMB90360 SeriesHARDWARE MANUAL

14CHAPTER 1 OVERVIEW1.5 Pin FunctionsTable 1.5-1 describes the pin functions of the MB90360 series. Pin FunctionsTable 1.5-1 Pin Description (1/3)P

284CHAPTER 16 8-/16-BIT PPG TIMER●8+8-bit PPG output operation modeThe 8 + 8-bit PPG output operation mode causes the PPGC of the 2-channel modules t

285CHAPTER 16 8-/16-BIT PPG TIMER16.2 Block Diagram of 8-/16-bit PPG TimerThe MB90360 series contains two 8-/16-bit PPG timers (each with 2 channels)

286CHAPTER 16 8-/16-BIT PPG TIMER16.2.1 Block Diagram for 8-/16-bit PPG Timer CThe 8-/16-bit PPG timer C consists of the following blocks. Block Dia

287CHAPTER 16 8-/16-BIT PPG TIMER●Details of pins in block diagramTable 16.2-1 lists the actual pin names and interrupt request numbers of the 8-/16-

288CHAPTER 16 8-/16-BIT PPG TIMER16.2.2 Block Diagram of 8-/16-bit PPG Timer DThe 8-/16-bit PPG timer D consists of the following blocks. Block Diag

289CHAPTER 16 8-/16-BIT PPG TIMER●Details of pins in block diagramTable 16.2-2 lists the actual pin names and interrupt request numbers of the 8-/16-

290CHAPTER 16 8-/16-BIT PPG TIMER16.3 Configuration of 8-/16-bit PPG TimerThis section explains the pins, registers and interrupt factors of the 8-/1

291CHAPTER 16 8-/16-BIT PPG TIMER List of Registers and Reset Values of 8-/16-bit PPG TimerFigure 16.3-1 List of Registers and Reset Values of 8-/1

292CHAPTER 16 8-/16-BIT PPG TIMER16.3.1 PPGC Operation Mode Control Register (PPGCC)The PPGC operation mode control register (PPGC0) provides the fol

293CHAPTER 16 8-/16-BIT PPG TIMERTable 16.3-2 Functions of PPGC Operation Mode Control Register (PPGCC)Bit Name Functionbit7 PEN0: PPG0 operation e

15CHAPTER 1 OVERVIEW26 C I Capacity pin for stabilizing power supply. It should be connected to higher than or equal to 0.1 µF ceramic capacitor.27 X

294CHAPTER 16 8-/16-BIT PPG TIMER16.3.2 PPGD Operation Mode Control Register (PPGCD)The PPGD operation mode control register provides the following s

295CHAPTER 16 8-/16-BIT PPG TIMERTable 16.3-3 Functions of PPGD Operation Mode Control Register (PPGCD)Bit name Functionbit15 PEN1: PPG1 operation e

296CHAPTER 16 8-/16-BIT PPG TIMER16.3.3 PPGC/D Count Clock Select Register (PPGCD)The PPGC/D count clock select register selects the count clock of t

297CHAPTER 16 8-/16-BIT PPG TIMERTable 16.3-4 Functions of PPGC/D Count Clock Select Register (PPGCD)Bit Name Functionbit7 to bit5PCS2 to PCS0: PPG

298CHAPTER 16 8-/16-BIT PPG TIMER16.3.4 PPG Reload Registers (PRLLC/PRLHC, PRLLD/PRLHD)The value (reload value) from which the PPG down counter start

299CHAPTER 16 8-/16-BIT PPG TIMER16.4 Interrupts of 8-/16-bit PPG TimerThe 8-/16-bit PPG timer can generate an interrupt request when the PPG down co

300CHAPTER 16 8-/16-BIT PPG TIMER16.5 Explanation of Operation of 8-/16-bit PPG TimerThe 8-/16-bit PPG timer outputs a pulse width at any frequency a

301CHAPTER 16 8-/16-BIT PPG TIMER16.5.1 8-bit PPG Output 2-channel Independent Operation ModeIn the 8-bit PPG output 2-channel independent operation

302CHAPTER 16 8-/16-BIT PPG TIMER●Operation in 8-bit PPG output 2-channel independent operation mode• The 8-bit PPG timer with two channels performs

303CHAPTER 16 8-/16-BIT PPG TIMER●Output waveform in 8-bit PPG output 2-channel independent operation modeThe High and Low pulse widths to be outputt

16CHAPTER 1 OVERVIEW45 P44 F General-purpose I/O port (I/O circuit type of P44 is different from that of MB90V340A.)FRCK0 Free-run timer 0 clock pin4

304CHAPTER 16 8-/16-BIT PPG TIMER16.5.2 16-bit PPG Output Operation ModeIn the 16-bit PPG output operation mode, the 8-/16-bit PPG timer is set as a

305CHAPTER 16 8-/16-BIT PPG TIMER●Operation in 16-bit PPG output operation mode• When either PPGn pin output or PPGm pin output is enabled (PPGCn:PEC

306CHAPTER 16 8-/16-BIT PPG TIMER●Output waveform in 16-bit PPG output operation modeThe High and Low pulse widths to be outputted are determined by

307CHAPTER 16 8-/16-BIT PPG TIMER16.5.3 8+8-bit PPG Output Operation ModeIn the 8 + 8-bit PPG output operation mode, the 8-/16-bit PPG timer is set a

308CHAPTER 16 8-/16-BIT PPG TIMER●Operation in 8+8-bit PPG output operation mode• The PPGn operates as the prescaler of the PPGm timer and the PPGm o

309CHAPTER 16 8-/16-BIT PPG TIMER●Output waveform in 8+8-bit PPG output operation modeThe High and Low pulse widths to be outputted are determined by

310CHAPTER 16 8-/16-BIT PPG TIMER16.6 Precautions when Using 8-/16-bit PPG TimerThis section explains the precautions when using the 8-/16-bit PPG ti

311CHAPTER 16 8-/16-BIT PPG TIMERFigure 16.6-1 Waveform when Values in PPG Reload Registers Rewritten Using Byte Instruction●Setting of PPG reload r

312CHAPTER 16 8-/16-BIT PPG TIMERFigure 16.6-2 Reload Timing in 16-bit PPG Output Operation ModeReload value of PPGmReload value of PPGnOnly 16-bit

313CHAPTER 17DTP/EXTERNALINTERRUPTSThis chapter explains the functions and operations of DTP/external interrupt.17.1 Overview of DTP/External Interru

17CHAPTER 1 OVERVIEW1.6 Input-Output CircuitsTable 1.6-1 lists the input-output circuits. Input-output CircuitsTable 1.6-1 I/O Circuit Types (1/4)T

314CHAPTER 17 DTP/EXTERNAL INTERRUPTS17.1 Overview of DTP/External InterruptThe DTP/external interrupt sends interrupt requests from external periphe

315CHAPTER 17 DTP/EXTERNAL INTERRUPTS17.2 Block Diagram of DTP/External InterruptThe block diagram of the DTP/external interrupt is shown below. Blo

316CHAPTER 17 DTP/EXTERNAL INTERRUPTS●DTP/external interrupt input detection circuitThis circuit detects interrupt requests or data transfer requests

317CHAPTER 17 DTP/EXTERNAL INTERRUPTS17.3 Configuration of DTP/External InterruptThis section lists and details the pins, interrupt factors, and regi

318CHAPTER 17 DTP/EXTERNAL INTERRUPTS List of Registers and Reset Values in DTP/External InterruptFigure 17.3-1 List of Registers and Reset Values

319CHAPTER 17 DTP/EXTERNAL INTERRUPTS17.3.1 DTP/External Interrupt Factor Register (EIRR1)The DTP/external interrupt factor register holds DTP/extern

320CHAPTER 17 DTP/EXTERNAL INTERRUPTSTable 17.3-2 Function of DTP/External Interrupt Factor Register (EIRR1)Bit Name Functionbit8tobit15ER15 to ER8(

321CHAPTER 17 DTP/EXTERNAL INTERRUPTS17.3.2 DTP/External Interrupt Enable Register (ENIR1)The DTP/external interrupt enable register (ENIR1) enables/

322CHAPTER 17 DTP/EXTERNAL INTERRUPTSTable 17.3-4 Correspondence between DTP/External Interrupt Pins, DTP/External Interrupt Request Flag Bits, and

323CHAPTER 17 DTP/EXTERNAL INTERRUPTS17.3.3 Detection Level Setting Register (ELVR1)The detection level setting register sets the level or edge of in

18CHAPTER 1 OVERVIEWE CMOS hysteresis input pinPull-up resister value: approx. 50 kΩF CMOS level output(IOL = 4 mA, IOH =-4 mA)CMOS hysteresis inputs

324CHAPTER 17 DTP/EXTERNAL INTERRUPTSTable 17.3-6 Correspondence between Detection Level Setting Register and ChannelsDTP/External Interrupt Pin Reg

325CHAPTER 17 DTP/EXTERNAL INTERRUPTS17.3.4 External Interrupt Factor Select Register (EISSR)The external interrupt factor select register (EISSR) ca

326CHAPTER 17 DTP/EXTERNAL INTERRUPTSTable 17.3-8 External Interrupt Factor Select (Upper 8-bit)EISSR Bit "0" (Initial Value) "1"

327CHAPTER 17 DTP/EXTERNAL INTERRUPTS17.4 Explanation of Operation of DTP/External InterruptThe DTP/external interrupt has an external interrupt func

328CHAPTER 17 DTP/EXTERNAL INTERRUPTS●Setting procedureTo use the DTP/external interrupt, set each register by using the following procedure:1. Set t

329CHAPTER 17 DTP/EXTERNAL INTERRUPTS DTP/External Interrupt OperationThe control bits and the interrupt factors for the DTP/external interrupt are

330CHAPTER 17 DTP/EXTERNAL INTERRUPTSFigure 17.4-2 Operation of DTP/External InterruptICR:ISE01ELVR1EIRR1ENIR1ICR YYICR XXCMPILILMCMPCPURecovery fro

331CHAPTER 17 DTP/EXTERNAL INTERRUPTS17.4.1 External Interrupt FunctionThe DTP/external interrupt has an external interrupt function for generating a

332CHAPTER 17 DTP/EXTERNAL INTERRUPTS17.4.2 DTP FunctionThe DTP/external interrupt has the DTP function that detects the signal of the external perip

333CHAPTER 17 DTP/EXTERNAL INTERRUPTS17.5 Precautions when Using DTP/External InterruptThis section explains the precautions when using the DTP/exter

19CHAPTER 1 OVERVIEWH CMOS level output(IOL = 4 mA, IOH =-4 mA)CMOS hysteresis inputs(with the standby-time input shutdown function)Automotive input(

334CHAPTER 17 DTP/EXTERNAL INTERRUPTS●Precautions on interrupts• When the DTP/external interrupt is used as the external interrupt function, no retur

335CHAPTER 17 DTP/EXTERNAL INTERRUPTS17.6 Program Example of DTP/External Interrupt FunctionThis section gives a program example of the DTP/external

336CHAPTER 17 DTP/EXTERNAL INTERRUPTS ÅE Processing by user ÅE RETI ;Return from interrupt processingCOD

337CHAPTER 17 DTP/EXTERNAL INTERRUPTS;;---------Main program-------------------------------------CODE CSEGSTART: ;Stack pointer (SP

338CHAPTER 17 DTP/EXTERNAL INTERRUPTS#26(1AH) DSL WARI ORG 00FFDCH ;Reset vector set DSL START DB 00H

339CHAPTER 188-/10-BIT A/D CONVERTERThis chapter explains the functions and operation of 8-/10-bit A/D converter.18.1 Overview of 8-/10-bit A/D Conve

340CHAPTER 18 8-/10-BIT A/D CONVERTER18.1 Overview of 8-/10-bit A/D ConverterThe 8-/10-bit A/D converter converts the analog input voltage to a 8- or

341CHAPTER 18 8-/10-BIT A/D CONVERTER18.2 Block Diagram of 8-/10-bit A/D ConverterThe 8-/10-bit A/D converter consists of following blocks. Block Di

342CHAPTER 18 8-/10-BIT A/D CONVERTER●Details of pins in block diagramTable 18.2-1 shows the actual pin names and interrupt request numbers of the 8-

343CHAPTER 18 8-/10-BIT A/D CONVERTER●Analog channel selectorThis selector selects the pin to be used for A/D conversion from the 16-channel analog i

20CHAPTER 1 OVERVIEWK CMOS level output(IOL = 4 mA, IOH = -4 mA)CMOS hysteresis inputs(with the standby-time input shutdown function)Automotive hyste

344CHAPTER 18 8-/10-BIT A/D CONVERTER18.3 Configuration of 8-/10-bit A/D ConverterThis section explains the pins, registers, and interrupt factors of

345CHAPTER 18 8-/10-BIT A/D CONVERTER List of Registers and Reset Values of 8-/10-bit A/D ConverterFigure 18.3-1 List of Register and Reset Value o

346CHAPTER 18 8-/10-BIT A/D CONVERTER18.3.1 A/D Control Status Register (High) (ADCS1)The A/D control status register (High) (ADCS1) provides the fol

347CHAPTER 18 8-/10-BIT A/D CONVERTERTable 18.3-2 Function of Each Bit of A/D Control Status Register (High) (ADCS1) (1/2)Bit name Functionbit15 BUS

348CHAPTER 18 8-/10-BIT A/D CONVERTERbit12 PAUS:Pause flag bitThis bit indicates the A/D conversion operating state when the EI2OS function is used.•

349CHAPTER 18 8-/10-BIT A/D CONVERTER18.3.2 A/D Control Status Register (Low) (ADCS0)The A/D control status register (Low) (ADCS0) provides the follo

350CHAPTER 18 8-/10-BIT A/D CONVERTERTable 18.3-3 Function of Each Bit of A/D Control Status Register (Low) (ADCS0)Bit Name Functionbit7bit6MD1, MD0

351CHAPTER 18 8-/10-BIT A/D CONVERTER18.3.3 A/D Data Register (ADCR0/ADCR1)The A/D data register (ADCR0/ADCR1) stores the digital value generated as

352CHAPTER 18 8-/10-BIT A/D CONVERTER18.3.4 A/D Setting Register (ADSR0/ADSR1)A/D setting register (ADSR0/ADSR1) can set as following. • Setting of A

353CHAPTER 18 8-/10-BIT A/D CONVERTERTable 18.3-5 Function of A/D Setting Register (ADSR0/ADSR1) (1/2)Bit Name Functionbit15 to bit13ST2, ST1, ST0:

21CHAPTER 1 OVERVIEW1.7 Handling DeviceThis section explains notes on handling the MB90360 series. Handling the Device●Preventing latch-upCMOS IC ch

354CHAPTER 18 8-/10-BIT A/D CONVERTERNote:Do not set the A/D conversion mode set bits (MD1 and MD0) and A/D conversion end channel select bits (ANE3,

355CHAPTER 18 8-/10-BIT A/D CONVERTERThe sampling time must be set according to drive impedance Rext connected to analog input. If thefollowing condi

356CHAPTER 18 8-/10-BIT A/D CONVERTER18.3.5 Analog Input Enable Register (ADER5, ADER6)The analog input enable register enables or disables the analo

357CHAPTER 18 8-/10-BIT A/D CONVERTERNotes:• When using as the analog input pin, write "1" to the bit of the analog input enable register (

358CHAPTER 18 8-/10-BIT A/D CONVERTER18.4 Interrupt of 8-/10-bit A/D ConverterWhen A/D conversion is terminated and its results are stored in the A/D

359CHAPTER 18 8-/10-BIT A/D CONVERTER18.5 Explanation of Operation of 8-/10-bit A/D ConverterThe 8-/10-bit A/D converter has the following A/D conver

360CHAPTER 18 8-/10-BIT A/D CONVERTER18.5.1 Single-shot Conversion ModeIn the single-shot conversion mode, A/D conversion is performed sequentially f

361CHAPTER 18 8-/10-BIT A/D CONVERTER Operation of Single-shot Conversion Mode• When the start trigger is inputted, A/D conversion starts from the c

362CHAPTER 18 8-/10-BIT A/D CONVERTER18.5.2 Continuous Conversion ModeIn the continuous conversion mode, A/D conversion is performed sequentially fro

363CHAPTER 18 8-/10-BIT A/D CONVERTER Operation of Continuous Conversion Mode• When the start trigger is inputted, A/D conversion starts from the ch

22CHAPTER 1 OVERVIEW●Using external clockTo use external clock, drive the X0 (X0A) pin and leave X1 (X1A) pin open.Figure 1.7-1 Using External Clock

364CHAPTER 18 8-/10-BIT A/D CONVERTER18.5.3 Pause-conversion ModeIn the pause-conversion mode, A/D conversion starts and pauses repeatedly for each c

365CHAPTER 18 8-/10-BIT A/D CONVERTER Operation of Pause-conversion Mode• When the start trigger is inputted, A/D conversion starts at the channel s

366CHAPTER 18 8-/10-BIT A/D CONVERTER18.5.4 Conversion Using EI2OS FunctionThe 8-/10-bit A/D converter can transfer the A/D conversion result to memo

367CHAPTER 18 8-/10-BIT A/D CONVERTER18.5.5 A/D-converted Data Protection FunctionA/D conversion with the output of an interrupt request enabled acti

368CHAPTER 18 8-/10-BIT A/D CONVERTERFigure 18.5-5 Processing Flow of A/D Conversion Data Protection Function when Using EI2OSNotes:• The A/D conver

369CHAPTER 18 8-/10-BIT A/D CONVERTER18.6 Precautions when Using 8-/10-bit A/D ConverterPrecautions when using the 8-/10-bit A/D converter are given

370CHAPTER 18 8-/10-BIT A/D CONVERTER

371CHAPTER 19LOW VOLTAGE DETECTION/CPU OPERATINGDETECTION RESETThis chapter explains the function and operating the low voltage detection/CPU operatin

372CHAPTER 19 LOW VOLTAGE DETECTION/CPU OPERATING DETECTION RESET19.1 Overview of Low Voltage/CPU Operating Detection Reset CircuitThe low voltage de

373CHAPTER 19 LOW VOLTAGE DETECTION/CPU OPERATING DETECTION RESET CPU Operating Detection Reset CircuitCPU operating detection reset circuit is a co

23CHAPTER 1 OVERVIEWFigure 1.7-2 Power Supply Pins (VCC/VSS)●Pull-up/down resistorsThe MB90360 Series does not support internal pull-up/down resisto

374CHAPTER 19 LOW VOLTAGE DETECTION/CPU OPERATING DETECTION RESET19.2 Configuration of Low Voltage/CPU Operating Detection Reset CircuitLow voltage/C

375CHAPTER 19 LOW VOLTAGE DETECTION/CPU OPERATING DETECTION RESET●CPU operating detection circuitIt is a counter for preventing the program out of co

376CHAPTER 19 LOW VOLTAGE DETECTION/CPU OPERATING DETECTION RESET19.3 Low Voltage/CPU Operating Detection Reset Circuit RegisterThis register clears

377CHAPTER 19 LOW VOLTAGE DETECTION/CPU OPERATING DETECTION RESETTable 19.3-1 Functional Description of Low Voltage/CPU operating Detection Reset Co

378CHAPTER 19 LOW VOLTAGE DETECTION/CPU OPERATING DETECTION RESET19.4 Operating of Low Voltage/CPU Operating Detection Reset CircuitThe circuit watch

379CHAPTER 19 LOW VOLTAGE DETECTION/CPU OPERATING DETECTION RESET19.5 Notes on Using Low Voltage/CPU Operating Detection Reset CircuitThis section ex

380CHAPTER 19 LOW VOLTAGE DETECTION/CPU OPERATING DETECTION RESET19.6 Sample Program for Low Voltage/CPU Operating Detection Reset CircuitThis sectio

381CHAPTER 20LIN-UARTThis chapter explains the functions and operation of LIN-UART.20.1 Overview of LIN-UART20.2 Configuration of LIN-UART20.3 LIN-

382CHAPTER 20 LIN-UART20.1 Overview of LIN-UARTThe LIN-UART with LIN (Local Interconnect Network) - Function is a general-purpose serial data communi

383CHAPTER 20 LIN-UARTLIN bus option• Master device operation• Slave device operation• LIN Synch break detection• LIN Synch break generation• Detecti

24CHAPTER 1 OVERVIEW●Notes on EnergizationTo prevent malfunction of the internal voltage regulator, supply voltage profile while turning on the power

384CHAPTER 20 LIN-UART LIN-UART operation modesThe LIN-UART operates in four different modes, which are determined by the MD0- and the MD1-bit ofthe

385CHAPTER 20 LIN-UART LIN-UART interrupt and EI2OSTable 20.1-4 LIN-UART Interrupt and EI2OSChannel Interrupt numberInterrupt control register Vect

386CHAPTER 20 LIN-UART20.2 Configuration of LIN-UARTThis section provides a short overview on the building blocks of LIN-UART. LIN-UART consists of t

387CHAPTER 20 LIN-UART Block Diagram of LIN-UARTFigure 20.2-1 Block Diagram of LIN-UARTRDRnTDRnPENPSBLCLA/DCRERXETXEMD1MD0OTOEXTRESTUSCKEUSOEPEOREF

388CHAPTER 20 LIN-UART Explanation of the different blocks●Reload CounterThe reload counter is a 15-bit reload counter that functions as the dedicat

389CHAPTER 20 LIN-UART●Oversampling CircuitThe oversampling circuit oversamples the incoming data at the SINn pin for five times in the asynchronousm

390CHAPTER 20 LIN-UART●Serial Control Register (SCR)This register performs the following operations:• Specifying whether to provide parity bits• Sele

391CHAPTER 20 LIN-UART20.3 LIN-UART PinsThis section describes the LIN-UART pins and provides a pin block diagram. LIN-UART PinsThe LIN-UART pins al

392CHAPTER 20 LIN-UART20.4 LIN-UART RegistersThe following figure shows the LIN-UART registers. LIN-UART RegistersFigure 20.4-1 LIN-UART Registers•

393CHAPTER 20 LIN-UART20.4.1 Serial Control Register (SCR)This register specifies parity bits, selects the stop bit and data lengths, selects a frame

25CHAPTER 1 OVERVIEW●Flash security FunctionThe security bit is located in the area of the flash memory.If protection code 01H is written in the secu

394CHAPTER 20 LIN-UARTTable 20.4-1 Function of Each Bit in Serial Control Register (SCR)No. Bit Name Functionbit15 PEN: Parity enable bitThis bit se

395CHAPTER 20 LIN-UART20.4.2 LIN-UART Serial Mode Register (SMR)This register selects an operation mode and baud rate clock and specifies whether to

396CHAPTER 20 LIN-UARTTable 20.4-2 Function of Each Bit in Serial Mode Register (SMR)No. Bit name Functionbit7,bit6MD1, MD0: Operation mode setting

397CHAPTER 20 LIN-UART20.4.3 Serial Status Register (SSR)This register checks the transmission and reception status and error status, and enables and

398CHAPTER 20 LIN-UARTTable 20.4-3 Function of Each Bit in Serial Status Register (SSR)No. Bit name Functionbit15 PE: Parity error flag bit•This bit

399CHAPTER 20 LIN-UART20.4.4 Reception and Transmission Data Register (RDR/TDR)Both RDR and TDR registers are located at the same address. At reading

400CHAPTER 20 LIN-UART Transmission Data Register (TDR)TDR is the data buffer register for serial data transmission. When data to be transmitted is

401CHAPTER 20 LIN-UART20.4.5 Extended Status/Control Register (ESCR)This register provides several LIN functions, direct access to the SINn and SOTn

402CHAPTER 20 LIN-UART*: Refer to the following table. Table 20.4-4 Function in Each Bit of the Extended Status/control Register (ESCR)NO. Bit name

403CHAPTER 20 LIN-UART20.4.6 Extended Communication Control Register (ECCR)The extended communication control register (ECCR) provides bus idle detec

26CHAPTER 1 OVERVIEW

404CHAPTER 20 LIN-UARTTable 20.4-6 Function of Each Bit in the Extended Communication Control Register (ECCR)NO. Bit name Functionbit7 Unused bit Th

405CHAPTER 20 LIN-UART20.4.7 Baud Rate Generator Register 0 and 1 (BGR0/1)The baud rate generator registers set the division ratio for the serial clo

406CHAPTER 20 LIN-UART20.5 LIN-UART InterruptsLIN-UART uses both reception and transmission interrupts. An interrupt request can be generated for eit

407CHAPTER 20 LIN-UART●Reception InterruptIf one of the following events occurs in reception mode, the corresponding flag bit of the serial statusreg

408CHAPTER 20 LIN-UART●LIN Synchronization Field Edge Detection InterruptsThis paragraph is only relevant, if LIN-UART operates in mode 3 as a LIN sl

409CHAPTER 20 LIN-UART20.5.1 Reception Interrupt Generation and Flag Set TimingThe following are the reception interrupt causes: completion of recept

410CHAPTER 20 LIN-UARTFigure 20.5-2 ORE Flag Set Timing:RDRFOREReception data

411CHAPTER 20 LIN-UART20.5.2 Transmission Interrupt Generation and Flag Set TimingA transmission interrupt is generated when the transmission data is

412CHAPTER 20 LIN-UART Transmission interrupt request generation timingIf the TDRE flag is set to "1" when a transmission interrupt is ena

413CHAPTER 20 LIN-UART20.6 LIN-UART Baud RatesOne of the following can be selected for the LIN-UART transmission/reception clock source:• Dedicated b

27CHAPTER 2CPUThis chapter explains the CPU.2.1 Outline of the CPU2.2 Memory Space2.3 Memory Map2.4 Linear Addressing2.5 Bank Addressing Types2.6

414CHAPTER 20 LIN-UARTFigure 20.6-1 Baud Rate Selection Circuit of LIN-UARTEXTRESTTxc = 0?Txc = v/2?OTO1010FFRxc = 0?Rxc = v/2?FFEXTOTO10CLKn=0,1D14

415CHAPTER 20 LIN-UART20.6.1 Setting the Baud RateThis section describes how the baud rates are set and the resulting serial clock frequency is calcu

416CHAPTER 20 LIN-UART Suggested division ratios for different machine speeds and baud ratesThe following settings are suggested for different MCU c

417CHAPTER 20 LIN-UART Using external clockIf the EXT bit of the SMR is set to 1, an external clock is selected, which has to be connected to the SC

418CHAPTER 20 LIN-UART20.6.2 Restarting the Reload CounterThe reload counter is a 15-bit reload counter that functions as dedicated baud rate generat

419CHAPTER 20 LIN-UARTNote:If LIN-UART is reset by setting SMR:UPCL to "1", the Reload Counters will restart too.• Automatic restart (recep

420CHAPTER 20 LIN-UART20.7 Operation of LIN-UARTLIN-UART operates in operation mode 0 for normal bidirectional serial communication, in mode 2 and 3

421CHAPTER 20 LIN-UART Inter-CPU Connection MethodExternal Clock One-to-one connection (normal mode) and master-slave connection (multiprocessor mod

422CHAPTER 20 LIN-UART20.7.1 Operation in Asynchronous Mode (Op. Modes 0 and 1)When LIN-UART is used in operation mode 0 (normal mode) or operation m

423CHAPTER 20 LIN-UARTFigure 20.7-1 Transfer Data Format (operation Modes 0 and 1)Note:If BDS bit of the Serial Status Register (SSR) is set to &quo

28CHAPTER 2 CPU2.1 Outline of the CPUThe F2MC-16LX CPU core is a 16-bit CPU designed for applications that require high-speed real-time processing, s

424CHAPTER 20 LIN-UART●Transmission operationIf the Transmission Data Register Empty (TDRE) flag bit of the Serial Status Register (SSR) is "1&q

425CHAPTER 20 LIN-UART●Stop bit1- or 2-stop bit can be selected at the transmission. When 2-stop bit is selected, both stop bits is detected atthe re

426CHAPTER 20 LIN-UART20.7.2 Operation in Synchronous Mode (Operation Mode 2)The clock synchronous transfer method is used for LIN-UART operation mod

427CHAPTER 20 LIN-UART●Clock supply:In operation mode 2, the number of clock cycles for the clock signal must be the same as the number of bitsfor th

428CHAPTER 20 LIN-UART●Communication:For initialization of the synchronous mode, following settings have to be done:Baud rate generator registers (BG

429CHAPTER 20 LIN-UART20.7.3 Operation with LIN Function (Operation Mode 3)LIN-UART can be used either as LIN-Master or LIN-Slave. For this LIN funct

430CHAPTER 20 LIN-UART where a is the value of the ICU data register after the first interrupt where b is the value of the

431CHAPTER 20 LIN-UARTFigure 20.7-8 LIN-UART Behavior as Slave in LIN Mode●LIN bus timingFigure 20.7-9 LIN Bus Timing and LIN-UART SignalsLBDSynch

432CHAPTER 20 LIN-UART20.7.4 Direct Access to Serial PinsLIN-UART allows the user to directly access to the transmission pin (SOTn) or the reception

433CHAPTER 20 LIN-UART20.7.5 Bidirectional Communication Function (Normal Mode)In operation mode 0 or 2, normal serial bidirectional communication is

29CHAPTER 2 CPU2.2 Memory SpaceAn F2MC-16LX CPU has a 16M bytes memory space. All data program input and output managed by the F2MC-16LX CPU are loca

434CHAPTER 20 LIN-UART●Communication procedureCommunication starts at arbitrary timing from the transmission side when the transmission data isprovid

435CHAPTER 20 LIN-UART20.7.6 Master-Slave Communication Function (Multiprocessor Mode)LIN-UART communication with multiple CPUs connected in master-s

436CHAPTER 20 LIN-UART●Function selectionSelect the operation mode and data transfer mode for master-slave communication as shown in Table 20.7-3 .●C

437CHAPTER 20 LIN-UARTFigure 20.7-15 Master-slave Communication FlowchartNOYESYESNONONOYESYESYESNO(Master CPU)(Slave CPU)Start StartSet operation mo

438CHAPTER 20 LIN-UART20.7.7 LIN Communication FunctionLIN-UART communication with LIN devices is available for both LIN master or LIN slave systems.

439CHAPTER 20 LIN-UART20.7.8 Sample Flowcharts for LIN-UART in LIN communication (Operation Mode 3)This section contains sample flowcharts for LIN-UA

440CHAPTER 20 LIN-UART LIN-UART as LIN slave deviceFigure 20.7-19 LIN-UART LIN Slave FlowchartYNNYYNYNYNStartInitial setting :Set operation mode 3S

441CHAPTER 20 LIN-UART20.8 Notes on Using LIN-UARTNotes on using LIN-UART are given below. Notes on Using LIN-UART●Enabling operations In LIN-UART,

442CHAPTER 20 LIN-UARTpredefined value.●Bus idle functionThe bus idle function cannot be used in synchronous mode 2.●AD bit (serial control register

443CHAPTER 21CAN CONTROLLERThis chapter explains the functions and operations of the CAN controller.21.1 Features of CAN Controller21.2 Block Diagra

30CHAPTER 2 CPU ROM area●Vector table area (address: FFFC00H to FFFFFFH)This area is used as a vector table for reset/interrupt and CALLV vector.Thi

444CHAPTER 21 CAN CONTROLLER21.1 Features of CAN ControllerThe CAN (Controller Area Network) is the standard protocol for serial communication betwee

44521.2 Block Diagram of CAN ControllerFigure 21.2-1 shows a block diagram of the CAN controller. Block Diagram of CAN ControllerFigure 21.2-1 Block

446CHAPTER 21 CAN CONTROLLER21.3 List of Overall Control RegistersFollowing Table lists the register. List of overall Control RegistersTable 21.3-1

447007D0CHRemote frame receive waiting registerRFWTR R/W XXXXXXXX XXXXXXXX007D0DH007D0EHTransmit interrupt enable registerTIER R/W 0 0 0 0 0 0 0 0 0

448CHAPTER 21 CAN CONTROLLER List of Message Buffers (ID registers)Table 21.3-2 List of Message Buffers (ID registers) (1 / 2)AddressRegister Abbre

449007C3CHID register 7 IDR7 R/WXXXXXXXX XXXXXXXX007C3DH007C3EHXXXXXXXX XXXXXXXX007C3FH007C40HID register 8 IDR8 R/WXXXXXXXX XXXXXXXX007C41H007C42HXXX

450CHAPTER 21 CAN CONTROLLER List of Message Buffers (DLC registers and data registers)Table 21.3-3 List of Message Buffer (DLC register and data r

451 List of Message Buffer (data register)Table 21.3-4 List of Message Buffer (data register)AddressRegister Abbreviation Access Initial ValueCAN100

452CHAPTER 21 CAN CONTROLLER21.4 Classifying CAN Controller RegistersThere are 3 types of CAN controller registers;• Overall control registers• Messa

45321.4.1 Configuration of Control Status Register (CSR)This register indicates bus operation, node status, transmit output enable and transmit/receiv

31CHAPTER 2 CPU Address generation typesThe F2MC-16LX has the following 2 addressing modes:●Linear addressing An entire 24-bit address is specified

454CHAPTER 21 CAN CONTROLLER21.4.2 Function of Control Status Register (CSR)The operating status of the register’s each bit is confirmed by following

455 Control status register (CSR-upper)Table 21.4-2 Function of Each Bit of the Control Status Register (CSR:H)Bit Name Functionbit15 TS: Transmit s

456CHAPTER 21 CAN CONTROLLER21.4.3 Correspondence between Node Status Bit and Node StatusNode status bit shows the node status by two bits (NS1 and N

45721.4.4 Notes on Using Bus Operation Stop Bit (HALT = 1)The bus operation stop bit is set by writing to the bit, hardware reset and the node status.

458CHAPTER 21 CAN CONTROLLER21.4.5 Last Event Indicator Register (LEIR)This register indicates the last event.The NTE, TCE, and RCE bits are exclusiv

459 Last Event Indicator Register (LEIR)Table 21.4-4 Function of Each Bit of the Last Event Indicator Register (LEIR) (1 / 2)Bit Name Functionbit7

460CHAPTER 21 CAN CONTROLLERbit3tobit0MBP3 to MBP0: Message buffer pointer bitsWhen TCE bit or RCE bit is "1", these bits show the message

46121.4.6 Receive and Transmit Error Counters (RTEC)The receive and transmit error counters indicate the counts for transmission errors and reception

462CHAPTER 21 CAN CONTROLLER21.4.7 Bit Timing Register (BTR)Bit timing register (BTR) sets the prescaler and bit timing setting. Register Configurat

46321.4.8 Prescaler Setting by Bit Timing Register (BTR)The setting of bit timing register (BTR) corresponds to the bit time of prescaler in the CAN s

32CHAPTER 2 CPU2.3 Memory MapThe memory map of the MB90360 Series is shown in Figure 2.3-1 . Memory MapThe ROM data in the high-order portion of FF-

464CHAPTER 21 CAN CONTROLLERThe relationship between PSC = PSC5 to PSC0, TSI = TS1.3 to TS1.0, TS2 = TS2.2 to TS2.0, and RSJ =RSJ1, RSJ0RSJ1 and RSJ0

46521.4.9 Message Buffer Valid Register (BVALR)Message buffer valid register (BVALR) stores the validity of the message buffers or displays their stat

466CHAPTER 21 CAN CONTROLLER21.4.10 IDE Register (IDER)This register stores the frame format used by the message buffers (x) during transmission/rece

46721.4.11 Transmission Request Register (TREQR)Transmission request register (TREQR) stores transmission requests to the message buffers (x) or displ

468CHAPTER 21 CAN CONTROLLER21.4.12 Transmission RTR Register (TRTRR)This register stores the RTR (Remote Transmission Request) bits for the message

46921.4.13 Remote Frame Receiving Wait Register (RFWTR)Remote frame receiving wait register (RFWTR) sets the conditions for starting transmission when

470CHAPTER 21 CAN CONTROLLER21.4.14 Transmission Cancel Register (TCANR)This register cancels a pending request for transmission to the message buffe

47121.4.15 Transmission Complete Register (TCR)At completion of transmission by the message buffer (x), the corresponding TCx becomes 1.If TIEx of the

472CHAPTER 21 CAN CONTROLLER21.4.16 Transmission Interrupt Enable Register (TIER)This register enables or disables the transmission interrupt by the

47321.4.17 Reception Complete Register (RCR)At completion of storing received message in the message buffer (x), RCx becomes 1.If RIEx of the receptio

33CHAPTER 2 CPU2.4 Linear AddressingThere are 2 types of linear addressing:• 24-bit operand specification: Directly specifies a 24-bit address using

474CHAPTER 21 CAN CONTROLLER21.4.18 Remote Request Receiving Register (RRTRR)After a remote frame is stored in the message buffer (x), RRTRx becomes

47521.4.19 Receive Overrun Register (ROVRR)If RCx of the reception complete register (RCR) is 1 when completing storing of a received message in the m

476CHAPTER 21 CAN CONTROLLER21.4.20 Reception Interrupt Enable Register (RIER)Reception interrupt enable register (RIER) enables or disables the rece

47721.4.21 Acceptance Mask Select Register (AMSR)This register selects masks (acceptance mask) for comparison between the received message ID’s and th

478CHAPTER 21 CAN CONTROLLER Register FunctionNotes:• AMSx.1 and AMSx.0 should be set when the message buffer (x) is invalid (BVALx of the messagebu

47921.4.22 Acceptance Mask Registers 0 and 1 (AMR0 and AMR1)There are two acceptance mask registers, which are available either in the standard frame

480CHAPTER 21 CAN CONTROLLERFigure 21.4-23 Configuration of the Acceptance Mask Register 1 (AMR1) Register Function●0: CompareCompare the bit (be s

48121.4.23 Message BuffersThere are 16 message buffers. Message buffer x (x = 0 to 15) consists of an ID register (IDRx), DLC register (DLCRx), and da

482CHAPTER 21 CAN CONTROLLER●Message buffer that can be used as multi level message bufferWhen the same receipt filter is set in 1 or more message bu

48321.4.24 ID Register x (x = 0 to 15) (IDRx)This register is the ID register for message buffer (x). Register ConfigurationFigure 21.4-24 Configura

iPREFACE Objectives and intended readerThank you very much for your continued patronage of Fujitsu semiconductor products.The MB90360 series has been

34CHAPTER 2 CPU2.5 Bank Addressing TypesIn the bank method, the 16M bytes space is divided into 256 for 64K bytes banks. The following 5 bank registe

484CHAPTER 21 CAN CONTROLLER Register FunctionWhen using the message buffer (x) in the standard frame format (IDEx of the IDE register (IDER) = 0),

48521.4.25 DLC Register x (x = 0 to 15) (DLCRx)This register is the DLC register for message buffer (x). Register ConfigurationFigure 21.4-25 Config

486CHAPTER 21 CAN CONTROLLER21.4.26 Data Register x (x = 0 to 15) (DTRx)This register is the data register for message buffer (x).This register is us

487 Register Function●Sets transmitted message data (any of 0 to 8 bytes).Data is transmitted in the order of BYTE0, BYTE1, ..., BYTE7, starting with

488CHAPTER 21 CAN CONTROLLER21.5 Transmission of CAN ControllerWhen 1 is written to TREQx of the transmission request register (TREQR), transmission

489 Completing Transmission of CAN ControllerWhen transmission is successful, RRTRx becomes 0, TREQx becomes 0, and TCx of the transmissioncomplete r

490CHAPTER 21 CAN CONTROLLER21.6 Reception of CAN ControllerReception starts when the start of data frame or remote frame (SOF) is detected on the CA

491Figure 21.6-1 shows a flowchart for determining the message buffer (x) where received messages are to bestored. It is recommended that message buff

492CHAPTER 21 CAN CONTROLLER Completing ReceptionRCx of the reception complete register (RCR) becomes 1 after storing the received message.If a rece

49321.7 Reception Flowchart of CAN ControllerFigure 21.7-1 shows a reception flowchart of the CAN controller. Reception Flowchart of the CAN Controll

35CHAPTER 2 CPUFigure 2.5-1 is an example of a memory space divided into register banks.Figure 2.5-1 Physical Addresses of Each SpaceTable 2.5-1 De

494CHAPTER 21 CAN CONTROLLER21.8 How to Use CAN ControllerThe following settings are required to use the CAN controller;•Bit timing• Frame format•ID•

495 Setting Low-power Consumption ModeTo set the F2MC-16LX in a low-power consumption mode (Stop and Timebase timer), write 1 to the busoperation sto

496CHAPTER 21 CAN CONTROLLER21.9 Procedure for Transmission by Message Buffer (x)After setting the bit timing, frame format, ID, and acceptance filte

497●Setting conditions for starting transmission (only for transmission of data frame)Set RFWTx of the remote frame receiving wait register (RFWTR) to

498CHAPTER 21 CAN CONTROLLER21.10 Procedure for Reception by Message Buffer (x)After setting the bit timing, frame format, ID, and acceptance filter,

499Figure 21.10-1 Example of Receive Interrupt HandlingEndRead received messages.A = 0?NOYESRCx:=0Interrupt with RCx = 1A:=ROVRxROVRx:=0

500CHAPTER 21 CAN CONTROLLER21.11 Setting Configuration of Multi-level Message BufferIf the receptions are performed frequently, or if several differ

501Figure 21.11-1 Examples of Operation of Multi-level Message BufferNote:Four messages are received with the same acceptance filter set in message b

502CHAPTER 21 CAN CONTROLLER21.12 Setting the CAN Direct Mode RegisterTo operate CAN normally, this register must be set correctly. CAN Direct Mode

50321.13 Precautions when Using CAN ControllerUse of the CAN Controller requires the following cautions. Caution for Disabling Message Buffers by BVA

36CHAPTER 2 CPU2.6 Multi-byte Data in Memory SpaceData is written to memory from the low-order addresses. Therefore, for a 32-bit data item, the low-

504CHAPTER 21 CAN CONTROLLER Setting of CAN Direct ModeMB90360 does not provide the clock modulation function. For this reason, ensure that theDIREC

505CHAPTER 22ADDRESS MATCHDETECTION FUNCTIONThis chapter explains the address match detection function and its operation.22.1 Overview of Address Mat

506CHAPTER 22 ADDRESS MATCH DETECTION FUNCTION22.1 Overview of Address Match Detection FunctionIf the address of the instruction to be processed next

507CHAPTER 22 ADDRESS MATCH DETECTION FUNCTION22.2 Block Diagram of Address Match Detection FunctionThe address match detection module consists of th

508CHAPTER 22 ADDRESS MATCH DETECTION FUNCTION22.3 Configuration of Address Match Detection FunctionThis section lists and details the registers used

509CHAPTER 22 ADDRESS MATCH DETECTION FUNCTION22.3.1 Address Detection Control Register (PACSR0/PACSR1)The address detection control register enables

510CHAPTER 22 ADDRESS MATCH DETECTION FUNCTIONTable 22.3-1 Functions of Address Detection Control Register (PACSR0)Bit Name Functionbit7,bit6Reserve

511CHAPTER 22 ADDRESS MATCH DETECTION FUNCTION Address Detection Control Register 1 (PACSR1)Figure 22.3-3 Address Detection Control Register 1 (PAC

512CHAPTER 22 ADDRESS MATCH DETECTION FUNCTIONTable 22.3-2 Functions of Address Detection Control Register (PACSR1)Bit Name Functionbit15,bit14Reser

513CHAPTER 22 ADDRESS MATCH DETECTION FUNCTION22.3.2 Detect Address Setting Registers (PADR0 to PADR5)The value of an address to be detected is set i

37CHAPTER 2 CPU2.7 RegistersThe F2MC-16LX registers are largely classified into two types: special registers in the CPU and general-purpose registers

514CHAPTER 22 ADDRESS MATCH DETECTION FUNCTION Functions of Detect Address Setting Registers• There are six detect address setting registers (PADR0

515CHAPTER 22 ADDRESS MATCH DETECTION FUNCTIONFigure 22.3-5 Setting of Starting Address of Instruction Code to be Replaced by INT9 InstructionNotes:

516CHAPTER 22 ADDRESS MATCH DETECTION FUNCTION22.4 Explanation of Operation of Address Match Detection FunctionIf the addresses of the instructions e

517CHAPTER 22 ADDRESS MATCH DETECTION FUNCTION22.4.1 Example of using Address Match Detection FunctionThis section gives an example of patch processi

518CHAPTER 22 ADDRESS MATCH DETECTION FUNCTION E2PROM Memory MapFigure 22.4-3 shows the allocation of the patch program and data at storing the patc

519CHAPTER 22 ADDRESS MATCH DETECTION FUNCTION Setting and Operating State●InitializationE2PROM data are all cleared to "00H".●Occurrence

520CHAPTER 22 ADDRESS MATCH DETECTION FUNCTION Operation of Address Match Detection Function at Storing Patch Program in E2PROMFigure 22.4-4 shows t

521CHAPTER 22 ADDRESS MATCH DETECTION FUNCTIONFigure 22.4-5 Flow of Patch Processing for Patch ProgramE2PROM : 0000H = 0INT9INT9NOYESNOYESMB90360ROM

522CHAPTER 22 ADDRESS MATCH DETECTION FUNCTION22.5 Program Example of Address Match Detection FunctionThis section gives a program example for the ad

523CHAPTER 22 ADDRESS MATCH DETECTION FUNCTION . RETI ;Return from interrupt processingCODE ENDS;---------Vector setting---------------

38CHAPTER 2 CPUFigure 2.7-1 Special RegistersAH ALAccumulatorUSPUser stack pointerSSPSystem stack pointerPSProcessor statusPCProgram counterDPRDirec

524CHAPTER 22 ADDRESS MATCH DETECTION FUNCTION

525CHAPTER 23ROM MIRRORING MODULEThis chapter describes the functions and operations of the ROM mirroring function select module.23.1 Overview of ROM

526CHAPTER 23 ROM MIRRORING MODULE23.1 Overview of ROM Mirroring Function Select ModuleThe ROM mirroring function select module provides a setting so

527CHAPTER 23 ROM MIRRORING MODULE Memory Space when ROM Mirroring Function Enabled/DisabledFigure 23.1-3 shows the availability of access to memory

528CHAPTER 23 ROM MIRRORING MODULE23.2 ROM Mirroring Function Select Register (ROMM)The ROM mirroring function select register (ROMM) enables or disa

529CHAPTER 24512K-BIT FLASH MEMORYThis chapter explains the functions and operation of the 512K-bit flash memory. The following three methods are avai

530CHAPTER 24 512K-BIT FLASH MEMORY24.1 Overview of 512K-bit Flash MemoryThe 512K-bit flash memory is mapped to the FFH bank in the CPU memory map. T

531CHAPTER 24 512K-BIT FLASH MEMORY24.2 Block Diagram of the Entire Flash Memory and Sector Configuration of the Flash MemoryFigure 24.2-1 shows a bl

532CHAPTER 24 512K-BIT FLASH MEMORYFigure 24.2-2 Sector Configuration of the 512K-bit Flash MemoryMB90F362/T(S),MB90F367/T(S)7FFFFH70000HFFFFFFHFF00

533CHAPTER 24 512K-BIT FLASH MEMORY24.3 Write/Erase ModesThe flash memory can be accessed in 2 different ways: Flash memory mode and alternative mode

39CHAPTER 2 CPU General-purpose registersThe F2MC-16LX general-purpose registers are located from addresses 000180H to 00037FH (maximumconfiguration

534CHAPTER 24 512K-BIT FLASH MEMORYTable 24.3-1 Flash Memory Control Signals (Developing: it is possible to change)MB90F362/T(S), MB90F367/T(S) MBM2

535CHAPTER 24 512K-BIT FLASH MEMORY24.4 Flash Memory Control Status Register (FMCS)This section shows the function of the flash memory control status

536CHAPTER 24 512K-BIT FLASH MEMORYNote:• The RDYINT and RDY bits cannot be changed at the same time. Create a program so that decisions aremade usin

537CHAPTER 24 512K-BIT FLASH MEMORYFigure 24.4-2 Transitions of the RDYINT and RDY BitsAutomatic algorithmend timingRDYINT bitRDY bit1 Machine cycle

538CHAPTER 24 512K-BIT FLASH MEMORY24.5 Starting the Flash Memory Automatic AlgorithmThree types of commands are available for starting the flash mem

539CHAPTER 24 512K-BIT FLASH MEMORY24.6 Confirming the Automatic Algorithm Execution StateBecause the write/erase flow of the flash memory is control

540CHAPTER 24 512K-BIT FLASH MEMORYTo determine whether automatic writing or chip erase is being executed, the hardware sequence flags canbe checked

541CHAPTER 24 512K-BIT FLASH MEMORY24.6.1 Data Polling Flag (DQ7)The data polling flag (DQ7) uses the data polling function to post that the automati

542CHAPTER 24 512K-BIT FLASH MEMORY24.6.2 Toggle Bit Flag (DQ6)Like the data polling flag (DQ7), the toggle bit flag (DQ6) uses the toggle bit functi

543CHAPTER 24 512K-BIT FLASH MEMORY24.6.3 Timing Limit Exceeded Flag (DQ5)The timing limit exceeded flag (DQ5) is used to post that execution of the

40CHAPTER 2 CPU2.7.1 Accumulator (A)The accumulator (A) register consists of 2 16-bit arithmetic operation registers (AH and AL), and is used as a te

544CHAPTER 24 512K-BIT FLASH MEMORY24.7 Detailed Explanation of Writing to and Erasing Flash MemoryThis section describes each operation procedure of

545CHAPTER 24 512K-BIT FLASH MEMORY24.7.1 Setting The Read/Reset StateThis section describes the procedure for issuing the Read/Reset command to set

546CHAPTER 24 512K-BIT FLASH MEMORY24.7.2 Writing DataThis section describes the procedure for issuing the Write command to write data to the flash m

547CHAPTER 24 512K-BIT FLASH MEMORYFigure 24.7-1 Example of the Flash Memory Write Procedure1YESDATANODATADATADATA0FMCS: WE (bit 5)Flash programming

548CHAPTER 24 512K-BIT FLASH MEMORY24.7.3 Erasing All Data (Erasing Chips)This section describes the procedure for issuing the Chip Erase command to

549CHAPTER 24 512K-BIT FLASH MEMORYFigure 24.7-2 Example of the Flash Memory Chip ProcedureNO1NOYESYES0FMCS: WE (bit 5)Flash programming enabledEras

550CHAPTER 24 512K-BIT FLASH MEMORY24.8 Notes on Using 512K-bit Flash MemoryThis section contains notes on using 512K-bit flash memory. Notes on Usi

551CHAPTER 24 512K-BIT FLASH MEMORY24.9 Flash Security FeatureFlash security feature provides possibilities to protect the content of the flash memor

552CHAPTER 24 512K-BIT FLASH MEMORY

553CHAPTER 25EXAMPLES OFMB90F362/T(S), MB90F367/T(S)SERIAL PROGRAMMINGCONNECTIONThis chapter shows an example of a serial programming connection using

41CHAPTER 2 CPU2.7.2 User Stack Pointer (USP) and System Stack Pointer (SSP)USP and SSP are 16-bit registers that indicate the memory addresses for s

554CHAPTER 25 EXAMPLES OF MB90F362/T(S), MB90F367/T(S) SERIAL PROGRAMMING CONNECTION25.1 Basic Configuration of Serial Programming Connection with MB

555CHAPTER 25 EXAMPLES OF MB90F362/T(S), MB90F367/T(S) SERIAL PROGRAMMING CONNECTIONEven if the P83, P84, SIN1, SOT1, and SCK1 pins are used for the

556CHAPTER 25 EXAMPLES OF MB90F362/T(S), MB90F367/T(S) SERIAL PROGRAMMING CONNECTIONprogrammer)Note:Although the AF200 flash microcontroller programm

557CHAPTER 25 EXAMPLES OF MB90F362/T(S), MB90F367/T(S) SERIAL PROGRAMMING CONNECTION25.2 Example of Serial Programming Connection (User Power Supply

558CHAPTER 25 EXAMPLES OF MB90F362/T(S), MB90F367/T(S) SERIAL PROGRAMMING CONNECTION• Even if the SIN1, SOT1, and SCK1 pins are used for the user sys

559CHAPTER 25 EXAMPLES OF MB90F362/T(S), MB90F367/T(S) SERIAL PROGRAMMING CONNECTION25.3 Example of Serial Programming Connection (Power Supplied fro

560CHAPTER 25 EXAMPLES OF MB90F362/T(S), MB90F367/T(S) SERIAL PROGRAMMING CONNECTION• Even if the SIN1, SOT1, and SCK1 pins are used for the user sys

561CHAPTER 25 EXAMPLES OF MB90F362/T(S), MB90F367/T(S) SERIAL PROGRAMMING CONNECTION25.4 Example of Minimum Connection to Flash Microcontroller Progr

562CHAPTER 25 EXAMPLES OF MB90F362/T(S), MB90F367/T(S) SERIAL PROGRAMMING CONNECTION• Even if the SIN1, SOT1, and SCK1 pins are used for the user sys

563CHAPTER 25 EXAMPLES OF MB90F362/T(S), MB90F367/T(S) SERIAL PROGRAMMING CONNECTION25.5 Example of Minimum Connection to Flash Microcontroller Progr

42CHAPTER 2 CPU2.7.3 Processor Status (PS)The PS register consists of the bits controlling the CPU operation and the bits indicating the CPU status.

564CHAPTER 25 EXAMPLES OF MB90F362/T(S), MB90F367/T(S) SERIAL PROGRAMMING CONNECTION• Even if the SIN1, SOT1, and SCK1 pins are used for the user sys

565CHAPTER 26ROM SECURITY FUNCTIONThis chapter explains the ROM security function.26.1 Overview of ROM Security Function

566CHAPTER 26 ROM SECURITY FUNCTION26.1 Overview of ROM Security FunctionThe ROM security function protects the content of ROM. Overview of ROM Sec

567APPENDIXThe appendixes provide I/O maps, instructions, and other information.APPENDIX A I/O MapsAPPENDIX B InstructionsAPPENDIX C Timing Diagram

568APPENDIX APPENDIX A I/O MapsTable A-1 lists addresses to be assigned to the registers in the peripheral blocks. I/O Maps (00XX Addresses)Table A-

569APPENDIX A I/O Maps000019HReserved00001AHPort A direction register DDRA W Port AXXX0 0XXXB00001BH to 00001DHReserved00001EHPort 2 pull-up control

570APPENDIX 00004BHReserved00004CHPPGE operation mode control registerPPGCE W, R/W16-bitPPGE/F0 X 0 0 0 XX1B00004DHPPGF operation mode control regist

571APPENDIX A I/O Maps00009FHDelayed interrupt/release register DIRR R/WDelayed Interrupt Generation ModuleXXXXXXX0B0000A0HLow-power mode control reg

572APPENDIX 0000CAHExternal interrupt enable 1 ENIR1 R/WExternal Interrupt 10 0 0 0 0 0 0 0B0000CBHExternal interrupt request 1 EIRR1 R/WXXXXXXXXB000

573APPENDIX A I/O Maps I/O map (79XX - 7FXX addresses)Table A-2 I/O Map (7900H - 7FFFH) (1/3)Address Register Abbreviation Access Peripheral Initia

43CHAPTER 2 CPU●T: Sticky bit flag:1 is set in the T flag when there is at least one "1" in the data shifted out from the carry after execu

574APPENDIX 7950H to 795FHReserved7960HClock supervisor control register CSVCR R, R/W Clock supervisor0 0 0 1 1 1 0 0B7961H to 796DHReserved796EHCA

575APPENDIX A I/O MapsNote:Any write access to reserved addresses in I/O map should not be perfoermed. A read access to reserved address results in r

576APPENDIX APPENDIX B InstructionsAppendix B describes the instructions used by the F2MC-16LX.B.1 Instruction TypesB.2 AddressingB.3 Direct Addre

577APPENDIX B InstructionsB.1 Instruction TypesThe F2MC-16LX supports 351 types of instructions. Addressing is enabled by using an effective address

578APPENDIX B.2 AddressingWith the F2MC-16LX, the address format is determined by the instruction effective address field or the instruction code its

579APPENDIX B Instructions Effective Address FieldTable B.2-1 lists the address formats specified by the effective address field.Table B.2-1 Effect

580APPENDIX B.3 Direct AddressingAn operand value, register, or address is specified explicitly in direct addressing mode. Direct Addressing●Immedia

581APPENDIX B InstructionsFigure B.3-2 Example of Register Direct Addressing●Direct branch addressing (addr16)Specify an offset explicitly for the b

582APPENDIX ●Physical direct branch addressing (addr24)Specify an offset explicitly for the branch destination address. The size of the offset is 24

583APPENDIX B Instructions●Abbreviated direct addressing (dir)Specify the eight low-order bits of a memory address explicitly in an operand. Address

ii CHAPTER 10 I/O PORTSThis chapter explains the functions and operations of the I/O ports.CHAPTER 11 TIMEBASE TIMERThis chapter explains the funct

44CHAPTER 2 CPU Interrupt level mask register (ILM)The ILM register consists of three bits, indicating the CPU interrupt masking level. An interrupt

584APPENDIX ●I/O direct bit addressing (io:bp)Specify bits in physical addresses 000000H to 0000FFH explicitly. Bit positions are indicated by "

585APPENDIX B Instructions●Vector Addressing (#vct)Specify vector data in an operand to indicate the branch destination address. There are two sizes

586APPENDIX B.4 Indirect AddressingIn indirect addressing mode, an address is specified indirectly by the address data of an operand. Indirect Addre

587APPENDIX B InstructionsFigure B.4-2 Example of Register Indirect Addressing with Post Increment (@RWj+ j = 0 to 3)●Register indirect addressing

588APPENDIX ●Program counter indirect addressing with offset (@PC + disp16)Memory is accessed using the address indicated by (instruction address + 4

589APPENDIX B Instructions●Program counter relative branch addressing (rel)The address of the branch destination is a value determined by adding an 8

590APPENDIX Figure B.4-9 Example of Register List (rlst)●Accumulator indirect addressing (@A)Memory is accessed using the address indicated by the c

591APPENDIX B Instructions●Accumulator indirect branch addressing (@A)The address of the branch destination is the content (16 bits) of the low-order

592APPENDIX ●Indirect specification branch addressing (@eam)The address of the branch destination is the word data at the address indicated by eam.Fi

593APPENDIX B InstructionsB.5 Execution Cycle CountThe number of cycles required for instruction execution (execution cycle count) is obtained by add

45CHAPTER 2 CPU2.7.4 Program Counter (PC)The PC register is a 16-bit counter that indicates the low-order 16 bits of the memory address of an instruc

594APPENDIX Calculating the execution cycle countTable B.5-1 lists execution cycle counts and Table B.5-2 and Table B.5-3 summarize correction valu

595APPENDIX B InstructionsNote:When an external data bus is used, the cycle counts during which an instruction is made to wait byready input or autom

596APPENDIX B.6 Effective address fieldTable B.6-1 shows the effective address field. Effective Address FieldTable B.6-1 Effective Address FieldCod

597APPENDIX B InstructionsB.7 How to Read the Instruction ListTable B.7-1 describes the items used in the F2MC-16LX Instruction List, and Table B.7-2

598APPENDIX RMWIndicates whether the instruction is a Read Modify Write instruction (reading data from memory by the I instruction and writing the re

599APPENDIX B Instructions#imm4 4-bit immediate data#imm8 8-bit immediate data#imm16 16-bit immediate data#imm32 32-bit immediate dataext (imm8) 16-b

600APPENDIX B.8 F2MC-16LX Instruction ListTable B.8-1 to Table B.8-18 list the instructions used by the F2MC-16LX. F2MC-16LX Instruction ListNote:Se

601APPENDIX B InstructionsNote:See Table B.5-1 and Table B.5-2 for information on (a) to (d) in the table.Table B.8-2 38 Transfer Instructions (byte

602APPENDIX Note:See Table B.5-1 and Table B.5-2 for information on (a) to (d) in the table.Table B.8-3 42 Addition/subtraction Instructions (byte,

603APPENDIX B InstructionsNote:See Table B.5-1 and Table B.5-2 for information on (a) to (d) in the table.Note:See Table B.5-1 and Table B.5-2 for in

46CHAPTER 2 CPU2.8 Register BankA register bank consists of eight words. The register bank can be used as the following general-purpose registers for

604APPENDIX Note:See Table B.5-1 and Table B.5-2 for information on (a) to (d) in the table.Table B.8-6 11 Unsigned Multiplication/division Instruct

605APPENDIX B InstructionsNotes:• The execution cycle count found when an overflow occurs in a DIV or DIVW instruction may be a pre-operation count o

606APPENDIX Note:See Table B.5-1 and Table B.5-2 for information on (a) to (d) in the table.Table B.8-8 39 Logic 1 Instructions (byte, word)Mnemonic

607APPENDIX B InstructionsNote:See Table B.5-1 and Table B.5-2 for information on (a) to (d) in the table.Note:See Table B.5-1 and Table B.5-2 for in

608APPENDIX Note:See Table B.5-1 and Table B.5-2 for information on (a) to (d) in the table.Table B.8-12 18 Shift Instructions (byte, word, long wor

609APPENDIX B InstructionsNote:See Table B.5-1 and Table B.5-2 for information on (a) to (d) in the table.Table B.8-13 31 Branch 1 InstructionsMnemo

610APPENDIX Note:See Table B.5-1 and Table B.5-2 for information on (a) to (d) in the table.Table B.8-14 19 Branch 2 InstructionsMnemonic # RG B Ope

611APPENDIX B InstructionsNote:See Table B.5-1 and Table B.5-2 for information on (a) to (d) in the table.Table B.8-15 28 Other Control Instructions

612APPENDIX Note:See Table B.5-1 and Table B.5-2 for information on (a) to (d) in the table.Table B.8-16 21 Bit Operand InstructionsMnemonic # RG B

613APPENDIX B InstructionsNote:m: RW0 value (counter value), n: Loop countSee Table B.5-1 and Table B.5-2 for information on (a) to (d) in the table.

47CHAPTER 2 CPU2.8-1 . DPR is eight bits long, and is initialized to 01H by a reset. DPR can be read or written to by aninstruction.Figure 2.8-1 Gen

614APPENDIX B.9 Instruction MapEach F2MC-16LX instruction code consists of 1 or 2 bytes. Therefore, the instruction map consists of multiple pages. T

615APPENDIX B InstructionsFigure B.9-2 Correspondence between Actual Instruction Code and Instruction MapAn example of an instruction code is shown

616APPENDIX Table B.9-2 Basic Page MapBit operation instructionCharacterstring opera-tion instruction2-byte instructionea instruc-tion 1ea instruc-t

617APPENDIX B InstructionsTable B.9-3 Bit Operation Instruction Map (first byte = 6CH)

618APPENDIX Table B.9-4 Character String Operation Instruction Map (first byte = 6EH)

619APPENDIX B InstructionsTable B.9-5 2-byte Instruction Map (first byte = 6FH)MULMULWDIVUAAA

620APPENDIX Table B.9-6 ea Instruction 1 (first byte = 70H)Use prohibitedUse prohibitedUse prohibitedUse prohibitedUse prohibitedUse prohibitedUse p

621APPENDIX B InstructionsTable B.9-7 ea Instruction 2 (first byte = 71H)

622APPENDIX Table B.9-8 ea Instruction 3 (first byte = 72H)

623APPENDIX B InstructionsTable B.9-9 ea Instruction 4 (first byte = 73H)

48CHAPTER 2 CPU2.9 Prefix CodesPlacing a prefix code before an instruction partially changes the operation of the instruction. Three types of prefix

624APPENDIX Table B.9-10 ea Instruction 5 (first byte = 74H)

625APPENDIX B InstructionsTable B.9-11 ea Instruction 6 (first byte = 75H)

626APPENDIX Table B.9-12 ea Instruction 7 (first byte = 76H)

627APPENDIX B InstructionsTable B.9-13 ea Instruction 8 (first byte = 77H)

628APPENDIX Table B.9-14 ea Instruction 9 (first byte = 78H)

629APPENDIX B InstructionsTable B.9-15 MOVEA RWi, ea Instruction (first byte = 79H)

630APPENDIX Table B.9-16 MOV Ri, ea Instruction (first byte = 7AH)

631APPENDIX B InstructionsTable B.9-17 MOVW RWi, ea Instruction (first byte = 7BH)

632APPENDIX Table B.9-18 MOV Ri, ea Instruction (first byte = 7CH)

633APPENDIX B InstructionsTable B.9-19 MOVW ea, Rwi Instruction (first byte = 7DH)

49CHAPTER 2 CPU●MOV ILM,#imm8The instruction is executed normally, but the prefix affects the next instruction.●RETISSB is used regardless of the pre

634APPENDIX Table B.9-20 XCH Ri, ea Instruction (first byte = 7EH)

635APPENDIX B InstructionsTable B.9-21 XCHW RWi, ea Instruction (first byte = 7FH)

636APPENDIX APPENDIX C Timing Diagrams in Flash Memory ModeEach timing diagram for the external pins of the Flash devices in MB90360 series during Fl

637APPENDIX C Timing Diagrams in Flash Memory Mode Write, Data Polling, Read (WE control)Figure C-2 Write, Data Polling, Read (WE control)Note: • D

638APPENDIX Write, Data Polling, Read (CE control)Figure C-3 Timing Diagram for Write Access (CE control)Note: • Describes the last 2-bus cycle of

639APPENDIX C Timing Diagrams in Flash Memory Mode Chip Erase/sector Erase Command SequenceFigure C-4 Timing Diagram for Write Access (chip erasing

640APPENDIX Data PollingFigure C-5 Timing Diagram for Data PollingNote:DQ7 is valid data (The device terminates automatic operation). Toggle BitF

641APPENDIX C Timing Diagrams in Flash Memory Mode RY/BY Timing during Writing/erasingFigure C-7 Timing Diagram for Output of RY/BY Signal during W

642APPENDIX Enable Sector Protect/verify Sector ProtectFigure C-9 Enable Sector Protect/verify Sector ProtectAQ18 to AQ9AQ8, AQ2, AQ1MD0MD2OEWECED

643APPENDIX C Timing Diagrams in Flash Memory Mode Temporary Sector Protect CancellationFigure C-10 Temporary Sector Protect CancellationMD1CEWERY/

50CHAPTER 2 CPU●MOV ILM,#imm8The instruction is executed normally, but the prefix affects the next instruction.

644APPENDIX APPENDIX D List of Interrupt VectorsThe interrupt vector table to be referenced for interrupt processing is allocated to FFFC00H to FFFFF

645APPENDIX D List of Interrupt VectorsINT 31 ReservedICR100000BAHFFFF80HFFFF81HFFFF82HUnusedINT 32 ReservedFFFF7CHFFFF7DHFFFF7EHUnusedINT 33 Input c

646APPENDIX Interrupt Causes, Interrupt Vectors, and Interrupt Control RegistersTable D-2 summarizes the relationships among the interrupt causes,

647APPENDIX D List of Interrupt VectorsNote:For a peripheral module having two interrupt causes for one interrupt number, an EI2OS interrupt clearsig

648APPENDIX

649INDEXINDEXThe index follows on the next page.This is listed in alphabetic order.

650INDEXIndexNumerics16-bit Free-run TimerBlock Diagram of 16-bit Free-run Timer ...213Explanation of Operation of 16-bit Free-run Timer...

651INDEXAAAccumulator (A)... 40A/D Control Status RegisterA/D Control Status Register (High) (ADCS1)...

652INDEXBidirectional CommunicationBidirectional Communication Function ...433Bit TimingSetting Bit Timing...

653INDEXClock Supervisor Control RegisterClock Supervisor Control Register (CSVCR)... 113Clock SupplyCycle of Clock Supply...

51CHAPTER 2 CPU2.10 Interrupt Disable InstructionsInterrupt requests are not sampled for the following ten instructions: - MOV ILM,#imm8

654INDEXData Polling FlagData Polling Flag (DQ7) ...541Data ReadData Read by Read Access...

655INDEXCorrespondence between 16-bit Reload Timer Interrupt and EI2OS... 251Correspondence between Timebase Timer Interrupt

656INDEXSector Configuration of the 512K-bit Flash Memory...531Setting the Flash Memory to the

657INDEXPrecautions for Use of "DIV A,Ri" and "DIVW A,RWi" Instructions... 52Restrictions on Interrupt Disable Inst

658INDEXLIN-master-slave CommunicationLIN-master-slave Communication Function...438LIN-UARTBlock Diagram of LIN-UART...38

659INDEXMessage Buffer Control RegistersMessage Buffer Control Registers ... 452MicrocontrollerConnection of an Oscillator or an Ext

660INDEXPatch ProcessingFlow of Patch Processing for Patch Program...520Patch ProgramFlow of Patch Processing for Patch Program...520Pause-con

661INDEXPSCCRConfiguration of the PLL/Subclock Control Register (PSCCR)... 101PUCRBlock Diagram of Pull-up Co

662INDEXList of Registers and Reset Values of ROM Mirroring Function Select Module ...527ROM Mirroring Function Select RegisterROM

663INDEXSub-clockOscillation Stabilization Wait Time Timer of Subclock ... 277Sub-clock Mode...

52CHAPTER 2 CPU2.11 Precautions for Use of "DIV A, Ri" and "DIVW A, RWi" InstructionsSet "00H" in the bank register bef

664INDEXLIN-UART as LIN Master Device...439LIN-UART Baud Rate Selection...413LIN-UART Direct Pin Access ...

CM44-10136-1EFUJITSU SEMICONDUCTOR • CONTROLLER MANUALF2MCTM-16LX16-BIT MICROCONTROLLERMB90360 SeriesHARDWARE MANUALApril 2005 the first editionPublis

53CHAPTER 2 CPUExample:If "DIV A,R0" is executed with DTB = "053H" and RP = "03H", the address of R0 is "0180H&quo

iiiCHAPTER 25 EXAMPLES OF MB90F362/T(S), MB90F367/T(S) SERIAL PROGRAMMINGCONNECTIONThis chapter shows an example of a serial programming connection u

54CHAPTER 2 CPU

55CHAPTER 3INTERRUPTSThis chapter explains the interrupts and function and operation of the extended intelligent I/O service in the MB90360 series. 3.

56CHAPTER 3 INTERRUPTS3.1 Outline of InterruptsThe F2MC-16LX has interrupt functions that terminate the currently executing processing and transfer c

57CHAPTER 3 INTERRUPTS Software InterruptsInterrupts requested by executing the INT instruction are software interrupts. An interrupt request by the

58CHAPTER 3 INTERRUPTS ExceptionsException processing is basically the same as interrupt processing. When an exception is detected betweeninstructio

59CHAPTER 3 INTERRUPTS3.2 Interrupt VectorAn interrupt vector uses the same area for both hardware and software interrupts. For example, interrupt re

60CHAPTER 3 INTERRUPTSINT 25Timebase timer 3ICR070000B7HFFFF98HFFFF99HFFFF9AHUnusedINT 26External interrupt 8 to 11FFFF94HFFFF95HFFFF96HUnusedINT 27W

61CHAPTER 3 INTERRUPTS3.3 Interrupt Control Registers (ICR)The interrupt control registers are in the interrupt controller. Each interrupt control re

62CHAPTER 3 INTERRUPTS[bit 11, bit 3] ISE (extended intelligent I/O service enable bits)The ISE bit is readable and writable. In response to an inter

63CHAPTER 3 INTERRUPTS[bit 15 to bit 12, bit 7 to bit 4] ICS 3 to ICS 0 (extended intelligent I/O service channel select bits)ICS3 to ICS0 are write-

iv ©2005 FUJITSU LIMITED Printed in Japan• The contents of this document are subject to change without notice. Customers are advised to consult with

64CHAPTER 3 INTERRUPTS[bit 13, bit 12, bits 5, bit 4] S0 and S1 (extended intelligent I/O service status)S0 and S1 are read-only bits. The values set

65CHAPTER 3 INTERRUPTS3.4 Interrupt FlowFigure 3.4-1 shows the interrupt flow. Interrupt FlowFigure 3.4-1 Interrupt FlowSTARTISE = 1YesYesYesYesNoN

66CHAPTER 3 INTERRUPTSFigure 3.4-2 Register Saving during Interrupt Processing"L""H"MSB LSBAHPSPCALDPRDPBADBPCBWord (16 bits)SSP

67CHAPTER 3 INTERRUPTS3.5 Hardware InterruptsIn response to an interrupt request signal from an internal resource, the CPU pauses current program exe

68CHAPTER 3 INTERRUPTS3.5.1 Hardware Interrupt OperationAn internal resource that has the hardware interrupt request function has an interrupt reques

69CHAPTER 3 INTERRUPTS3.5.2 Occurrence and Release of Hardware InterruptFigure 3.5-1 shows the processing flow from occurrence of a hardware interrup

70CHAPTER 3 INTERRUPTSThe time required for the CPU to execute the interrupt processing in steps 6. and 7. is shown below.See Table 3.5-1 for the cyc

71CHAPTER 3 INTERRUPTS3.5.3 Multiple interruptsAs a special case, no hardware interrupt request can be accepted while data is being written to the I/

72CHAPTER 3 INTERRUPTS3.6 Software InterruptsIn response to execution of a special instruction, control is transferred from the program currently exe

73CHAPTER 3 INTERRUPTSFigure 3.6-1 Occurrence and Release of Software Interrupt(1) The software interrupt instruction is executed.(2) Special CPU re

vCONTENTSCHAPTER 1 OVERVIEW ... 11.1 Overview of MB90

74CHAPTER 3 INTERRUPTS3.7 Extended Intelligent I/O Service (EI2OS)The EI2OS function, a kind of hardware interrupt operation, automatically transfers

75CHAPTER 3 INTERRUPTSFigure 3.7-1 Outline of Extended Intelligent I/O ServiceNote:• The area that can be specified by IOA is between 000000H and 00

76CHAPTER 3 INTERRUPTS3.7.1 Extended Intelligent I/O Service Descriptor (ISD)The extended intelligent I/O service descriptor exists between 000100H a

77CHAPTER 3 INTERRUPTS I/O register address pointer (IOA)This is a 16-bit register that indicates the low-order address (A15 to A0) of the buffer an

78CHAPTER 3 INTERRUPTS3.7.2 EI2OS Status Register (ISCS)This eight-bit register indicates the update direction (increment/decrement), transfer data f

79CHAPTER 3 INTERRUPTS3.8 Operation Flow of and Procedure for Using the Extended Intelligent I/O Service (EI2OS)Figure 3.8-1 is a diagram of the EI2O

80CHAPTER 3 INTERRUPTSFigure 3.8-2 EI2OS Use FlowThe extended EI2OS execution time for each flow is described below.●When data transfer continues (w

81CHAPTER 3 INTERRUPTSTable 3.8-2 Data Transfer Compensation Values for EI2OS Execution TimeI/O address pointerInternal accessB/E OBuffer address po

82CHAPTER 3 INTERRUPTS3.9 ExceptionsThe F2MC-16LX performs exception processing when the following event occurs: Execution of an Undefined Instructi

83CHAPTER 4DELAYED INTERRUPTGENERATION MODULEThis chapter explains the functions and operations of the delayed interrupt generation module.4.1 Overvi